protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer netlistContainer = GetNetlistContainer();
// extract net names as we may not remve during iteration
List <XDLNet> netNamesToDecompose = new List <XDLNet>();
foreach (string netName in NetNames)
{
XDLNet n = (XDLNet)netlistContainer.GetNet(netName);
netNamesToDecompose.Add(n);
}
foreach (XDLNet net in netNamesToDecompose)
{
foreach (XDLPip pip in net.Pips)
{
XDLNet arc = new XDLNet(net.Name + "_" + pip.Location + "_" + pip.From + "_" + pip.To);
// TODO what about attributes
arc.Add(pip);
netlistContainer.Add(arc);
}
net.ClearPips();
if (net.NetPinCount == 0)
{
netlistContainer.Remove(new Predicate <Net>(n => n.Name.Equals(net.Name)));
}
}
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
// do not store addSlice in constructor already!
m_addedSlice = FPGA.FPGA.Instance.Current.Slices[SliceNumber];
/*
* if (netlistContainer.HasSlice(this.m_addedSlice))
* {
* this.OutputManager.WriteOutput("Overwriting slice " + this.m_addedSlice + " in macro " + netlistContainer);
* }*/
netlistContainer.Add(m_addedSlice);
}
private void RelocateNetsForTCL(LibraryElement libElement, Tile anchorCLB, NetlistContainer netlistContainer)
{
foreach (TCLNet net in libElement.Containter.Nets)
{
TCLNet relocatedNet = TCLNet.Relocate(net, libElement, anchorCLB);
relocatedNet.Name = InstanceName + relocatedNet.Name;
// relocate NetPins
foreach (NetPin pin in relocatedNet.NetPins)
{
if (InsertPrefix)
{
pin.InstanceName = InstanceName + pin.InstanceName;
}
}
netlistContainer.Add(relocatedNet);
}
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
foreach (Tile probe in TileSelectionManager.Instance.GetSelectedTiles())
{
if (probe.SwitchMatrix.GetAllArcs().Any(tupel => tupel.Item1.Name.Equals(From) && tupel.Item2.Name.Equals(To)))
{
XDLNet n = new XDLNet(probe.Location + "_" + From + "_" + To);
n.Add(CommentForPip);
n.Add(probe, new Port(From), new Port(To));
/*
* probe.BlockPort(new Port(this.From), false);
* probe.BlockPort(new Port(this.To), false);*/
netlistContainer.Add(n);
}
else
{
OutputManager.WriteOutput("Warning: Arc " + From + " -> " + To + " not found on tile " + probe.Location);
}
}
}
protected override void DoCommandAction()
{
BlockOnlyMarkedPortsScope = BlockOnlyMarkedPorts;
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
// prevent repeated error message from subcommands
if (!NetlistContainerManager.Instance.Contains(NetlistContainerName))
{
throw new ArgumentException("The netlist container " + NetlistContainerName + " does not exist. Use the command AddNetlistContainer to add a netlist container.");
}
NetlistContainer nlc = GetNetlistContainer();
Net blockerNet = null;
bool useExistingNet = false;
if (nlc.Nets.Any(n => n.OutpinCount > 0))
{
useExistingNet = true;
blockerNet = nlc.GetAnyNet();
OutputManager.WriteOutput("Adding blocker pips to already existing net " + blockerNet.Name);
}
else
{
// create XDL or TCL script
blockerNet = Net.CreateNet("BlockSelection");
if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.Vivado)
{
blockerNet = new TCLNet("BlockSelection");
//((TCLNet)blockerNet).Properties.SetProperty("IS_ROUTE_FIXED", "TRUE", false);
// tag for code generation
((TCLNet)blockerNet).IsBlockerNet = true;
((TCLNet)blockerNet).RoutingTree = new TCLRoutingTree();
TCLRoutingTreeNode root = new TCLRoutingTreeNode(null, null);
root.VirtualNode = true;
((TCLNet)blockerNet).RoutingTree.Root = root;
}
useExistingNet = false;
bool outPinAdded = false;
// the location string of the tile in which we run the outpin
string outpinLocation = "";
// 1 iterate over all not filtered out tiles to instantiate primitves and to find an outpin
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
AddXDLTemplates(nlc, blockerNet, ref outPinAdded, ref outpinLocation);
break;
case FPGATypes.BackendType.Vivado:
//this.AddTCLInstances(nlc, blockerNet, ref outPinAdded, ref outpinLocation);
((TCLContainer)nlc).AddGndPrimitive(blockerNet);
outPinAdded = true;
break;
}
// 2 name net according to added outpin
blockerNet.Name = Prefix + outpinLocation + "_" + blockerNet.Name;
if (!outPinAdded)
{
OutputManager.WriteOutput("Could not find an outpin");
}
}
// 4 cluster all completely unblocked tiles by their identifiers (do not cluster BEFORE having added and thus blocked an outpin)
// tiles with already blocked ports are added to single cluster each and thus treated seperately
Dictionary <int, List <Tile> > clusteredTiles = new Dictionary <int, List <Tile> >();
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
FindClusteringForISE(clusteredTiles);
break;
case FPGATypes.BackendType.Vivado:
FindClusteringForVivado(clusteredTiles);
break;
}
// block by
// 5 paths ...
int clusterCount = 0;
foreach (List <Tile> tiles in clusteredTiles.Values)
{
AddBlockerPaths(blockerNet, tiles[0], tiles);
ProgressInfo.Progress = 0 + (int)((double)clusterCount++ / (double)clusteredTiles.Count * 50);
}
// 6 and arcs
clusterCount = 0;
foreach (List <Tile> tiles in clusteredTiles.Values)
{
AddArcs(blockerNet, tiles[0], tiles);
ProgressInfo.Progress = 50 + (int)((double)clusterCount++ / (double)clusteredTiles.Count * 50);
}
// 7 check blocking
if (PrintUnblockedPorts)
{
foreach (Tile t in TileSelectionManager.Instance.GetSelectedTiles().Where(
t => !BlockerSettings.Instance.SkipTile(t) && IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.Interconnect)))
{
CheckForUnblockedPorts(t);
}
}
// clean up indeces
foreach (Tile tile in TileSelectionManager.Instance.GetSelectedTiles().Where(t => !BlockerSettings.Instance.SkipTile(t)))
{
tile.SwitchMatrix.ClearBlockingPortList();
}
// add prefix and store nets
if (blockerNet.PipCount > 0 && !useExistingNet)
{
nlc.Add(blockerNet);
}
}
protected override void DoCommandAction()
{
if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.Vivado)
{
return;
}
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer nlc = GetNetlistContainer();
int workload = GetNetsToDecomposeWithOutpin().Count();
int count = 0;
List <XDLNet> newNets = new List <XDLNet>();
foreach (XDLNet net in GetNetsToDecomposeWithOutpin().Where(n => n.PRLink))
{
ProgressInfo.Progress = ProgressStart + (int)((double)count++ / (double)workload * ProgressShare);
Dictionary <string, List <XDLPip> > pipsToRemove = null;
// decompose nets without outpin.
// e.g., placing a module on connection macros wil remove outpins from certain I/O bar wires
if (net.NetPins.Where(np => np is NetOutpin).Count() == 0)
{
pipsToRemove = new Dictionary <string, List <XDLPip> >();
foreach (XDLPip pip in net.Pips)
{
if (!pipsToRemove.ContainsKey(pip.Location))
{
pipsToRemove.Add(pip.Location, new List <XDLPip>());
}
pipsToRemove[pip.Location].Add(pip);
}
}
else
{
bool antenna = net.IsAntenna(out pipsToRemove);
}
bool firstArc = true;
// values are all non empty litst
foreach (List <XDLPip> l in pipsToRemove.Values)
{
foreach (XDLPip pip in l)
{
if (firstArc)
{
firstArc = false;
//this.OutputManager.WriteOutput("Decomposing net " + net.Name);
}
XDLNet arc = new XDLNet(net.Name + "_arc_" + pip.Location + "_" + pip.From + "_" + pip.To);
//arc.AddComment("decomposed from net (with outpin) " + net.Name);
// TODO what about attributes?
arc.Add(pip);
// move inpins
List <NetPin> netPinsToRemove = new List <NetPin>();
foreach (NetPin netpin in net.NetPins.Where(np => np is NetInpin))
{
XDLInstance inst = (XDLInstance)nlc.GetInstanceByName(netpin.InstanceName);
Tile pipTile = FPGA.FPGA.Instance.GetTile(pip.Location);
if (pipTile.TileKey.Equals(inst.TileKey))
{
//netpin.Comment += "taken from " + net.Name;
arc.Add(netpin);
// store net pip for later removal as we may not change the collection during iterating over it
netPinsToRemove.Add(netpin);
}
}
// remove the inpins from the original net ...
net.RemoveAllPinStatements(np => netPinsToRemove.Contains(np));
// ... and remove the arc from the original net
newNets.Add(arc);
}
}
// only invoke Remove once per net (blocker is very slow)
net.Remove(p => PipFilter(p, pipsToRemove));
}
// decompose blocker net
foreach (XDLNet net in GetNetsToDecomposeWithoutOutpin())
{
foreach (XDLPip pip in net.Pips)
{
XDLNet arc = new XDLNet(net.Name + "_arc_" + pip.Location + "_" + pip.From + "_" + pip.To);
//arc.AddComment("decomposed from net (without outpin) " + net.Name);
// TODO what about attributes?
arc.Add(pip);
newNets.Add(arc);
}
// remove all pips
net.ClearPips();
}
// add arcs
foreach (XDLNet n in newNets)
{
nlc.Add(n);
}
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
netlistContainer.Add(Net.CreateNet(NetName));
}
