private Tile GetTile(NetlistContainer container, NetPin pin)
{
Instance instance = container.GetInstanceByName(pin.InstanceName);
Tile instanceTile = FPGA.FPGA.Instance.GetTile(instance.Location);
return(instanceTile);
}
protected override void DoCommandAction()
{
NetlistContainer nlc = GetNetlistContainer();
int clbCount = 0;
int bramCount = 0;
int dspCount = 0;
TileSelectionManager.Instance.GetRessourcesInSelection(TileSelectionManager.Instance.GetSelectedTiles(), out clbCount, out bramCount, out dspCount);
int sliceCount = clbCount * 2;
int sliceInstances = 0;
int bramInstances = 0;
int dspInstances = 0;
foreach (XDLInstance inst in nlc.Instances.Where(i => TileSelectionManager.Instance.IsSelected(i.TileKey)))
{
if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.CLB))
{
sliceInstances++;
}
else if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.DSP))
{
dspInstances++;
}
else if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.BRAM))
{
bramInstances++;
}
}
OutputManager.WriteOutput("Slices: " + sliceInstances + " out of " + sliceCount);
OutputManager.WriteOutput("DSPs: " + dspInstances + " out of " + dspCount);
OutputManager.WriteOutput("BRAMs: " + bramInstances + " out of " + bramCount);
}
private bool AddArcsXDL(NetlistContainer netlistContainer)
{
// which net to extend?
XDLNet target;
if (netlistContainer.Nets.Any(n => n.Name.Equals(Netname)))
{
target = (XDLNet)netlistContainer.GetNet(Netname);
}
else
{
target = (XDLNet)netlistContainer.GetAnyNet();
}
Port from = new Port(From);
Port to = new Port(To);
bool arcAdded = false;
foreach (Tile t in TileSelectionManager.Instance.GetSelectedTiles().Where(t => AddArcOnThisTile(from, to, t)))
{
target.Add(CommentForPip);
target.Add(t, from, to);
if (!t.IsPortBlocked(from, Tile.BlockReason.Blocked))
{
t.BlockPort(from, Tile.BlockReason.Blocked);
}
t.BlockPort(to, Tile.BlockReason.Blocked);
arcAdded = true;
}
return(arcAdded);
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer netlistContainer = GetNetlistContainer();
// extract net names as we may not remve during iteration
List <XDLNet> netNamesToDecompose = new List <XDLNet>();
foreach (string netName in NetNames)
{
XDLNet n = (XDLNet)netlistContainer.GetNet(netName);
netNamesToDecompose.Add(n);
}
foreach (XDLNet net in netNamesToDecompose)
{
foreach (XDLPip pip in net.Pips)
{
XDLNet arc = new XDLNet(net.Name + "_" + pip.Location + "_" + pip.From + "_" + pip.To);
// TODO what about attributes
arc.Add(pip);
netlistContainer.Add(arc);
}
net.ClearPips();
if (net.NetPinCount == 0)
{
netlistContainer.Remove(new Predicate <Net>(n => n.Name.Equals(net.Name)));
}
}
}
protected override void DoCommandAction()
{
NetlistContainer macro = NetlistContainerManager.Instance.Get(MacroName);
// 1 iterate over all not filtered out tiles to instantiate primitves and to find an outpin
foreach (Tile t in TileSelectionManager.Instance.GetSelectedTiles().Where(t => !BlockerSettings.Instance.SkipTile(t)))
{
// iterate in order
for (int i = 0; i < t.Slices.Count; i++)
{
Slice s = t.Slices[i];
if (!Regex.IsMatch(i.ToString(), SliceNumberPattern) || s.Usage != FPGATypes.SliceUsage.Free)
{
continue;
}
string template = "";
// ignore the SliceNumberPattern given by AddBlockerPrimitveRegexp, this command has its own one
// TODO add AddPrimitveRegexp in addition to AddBlockerPrimitveRegexp
if (BlockerSettings.Instance.InsertTemplate(s.SliceName, true, i, out template))
{
AddTemplateConfig addTemplateCommand = new AddTemplateConfig();
addTemplateCommand.Location = t.Location;
addTemplateCommand.NetlistContainerName = NetlistContainerName;
addTemplateCommand.PrimitiveIndex = i;
addTemplateCommand.Template = template;
CommandExecuter.Instance.Execute(addTemplateCommand);
// attach usage
s.Usage = FPGATypes.SliceUsage.Blocker;
}
}
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
LibElemInst inst = LibraryElementInstanceManager.Instance.GetInstantiation(InstanceName);
LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName);
Tile anchorCLB = FPGA.FPGA.Instance.GetTile(inst.AnchorLocation);
NetlistContainer netlistContainer = GetNetlistContainer();
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
RelocateInstancesForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer);
RelocateNetsForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer);
// add design config
if (AddDesignConfig && libElement.Containter is XDLContainer && ((XDLContainer)netlistContainer).GetDesignConfig().Length == 0)
{
((XDLContainer)netlistContainer).AddDesignConfig(((XDLContainer)libElement.Containter).GetDesignConfig());
}
break;
case FPGATypes.BackendType.Vivado:
RelocateInstancesForTCL(libElement, anchorCLB, (TCLContainer)netlistContainer);
RelocateNetsForTCL(libElement, anchorCLB, netlistContainer);
break;
}
}
private void m_btnGenerate_Click(object sender, EventArgs e)
{
List <string> names = new List <string>();
foreach (object o in m_checkedListBoxNetlistContainer.SelectedItems)
{
NetlistContainer nlc = (NetlistContainer)o;
names.Add(nlc.Name);
}
GenerateXDL genCmd = new GenerateXDL();
genCmd.DesignName = m_txtDesignName.Text;
genCmd.FileName = m_fileSel.FileName;
genCmd.IncludeDesignStatement = m_chkIncludeDesignStatement.Checked;
genCmd.IncludeDummyNets = m_chkIncludeDummyNets.Checked;
genCmd.IncludeModuleFooter = m_chkIncludeFooter.Checked;
genCmd.IncludeModuleHeader = m_chkIncludeHeader.Checked;
genCmd.IncludePorts = m_chkIncludePorts.Checked;
genCmd.NetlistContainerNames = names;
genCmd.SortInstancesBySliceName = m_chkSort.Checked;
Commands.CommandExecuter.Instance.Execute(genCmd);
if (ParentForm != null)
{
ParentForm.Close();
}
}
protected override void DoCommandAction()
{
FPGA.FPGATypes.AssertBackendType(FPGA.FPGATypes.BackendType.ISE);
NetlistContainer netlistContainer = GetNetlistContainer();
Regex sourceNetFilter = new Regex(SourceNetsRegexp, RegexOptions.Compiled);
Regex targetNetFilter = new Regex(TargetNetsRegexp, RegexOptions.Compiled);
Regex pipFilter = new Regex(PipFilter, RegexOptions.Compiled);
XDLNet targetNet = (XDLNet)netlistContainer.Nets.FirstOrDefault(n => targetNetFilter.IsMatch(n.Name));
if (targetNet == null)
{
throw new ArgumentException("Could not find a target net");
}
foreach (XDLNet sourceNet in netlistContainer.Nets.Where(n => sourceNetFilter.IsMatch(n.Name)))
{
foreach (XDLPip pip in sourceNet.Pips.Where(p => pipFilter.IsMatch(p.Location)))
{
XDLPip copy = new XDLPip(pip.Location, pip.From, pip.Operator, pip.To);
targetNet.Add(copy);
}
}
}
private void GetSourceAndSink(NetlistContainer container, XDLNet net, out Tile source, out Tile sink)
{
// where is the outpin
NetOutpin outPin = (NetOutpin)net.NetPins.Where(p => p is NetOutpin).First();
source = GetTile(container, outPin);
List <Tile> tilesWithInpins = new List <Tile>();
if (TileSelectionManager.Instance.IsSelected(source.TileKey))
{
foreach (NetPin pin in net.NetPins.Where(p => p is NetInpin && !IsInside(container, p)))
{
tilesWithInpins.Add(GetTile(container, pin));
}
}
else
{
foreach (NetPin pin in net.NetPins.Where(p => p is NetInpin && IsInside(container, p)))
{
tilesWithInpins.Add(GetTile(container, pin));
}
}
double x, y;
TileSelectionManager.Instance.GetCenterOfTiles(tilesWithInpins, out x, out y);
sink = FPGA.FPGA.Instance.GetTile((int)x, (int)y);
}
protected override void DoCommandAction()
{
NetlistContainer nlc = GetNetlistContainer();
foreach (XDLNet net in nlc.Nets.Where(n => n.OutpinCount == 1 && n.InpinCount > 0 && n.PipCount == 0))
{
OutputManager.WriteOutput(net.Name);
}
}
public IEnumerable <XDLNet> GetAllNets()
{
NetlistContainer nlc = GetNetlistContainer();
foreach (XDLNet net in nlc.Nets.Where(n => Positive((XDLNet)n) && !Negative((XDLNet)n)))
{
yield return(net);
}
}
private IEnumerable <XDLNet> GetNetsToDecomposeWithoutOutpin()
{
NetlistContainer macro = GetNetlistContainer();
foreach (XDLNet net in macro.Nets.Where(n => n.OutpinCount == 0 && n.InpinCount == 0 && n.PipCount > 0))
{
yield return(net);
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer netlistContainer = GetNetlistContainer();
foreach (XDLNet n in netlistContainer.Nets)
{
foreach (XDLPip pip in n.Pips)
{
Tile t = FPGA.FPGA.Instance.GetTile(pip.Location);
if (!IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))
{
continue;
}
foreach (Slice s in t.Slices)
{
bool inport = s.PortMapping.IsSliceInPort(new Port(pip.To));
bool outport = s.PortMapping.IsSliceOutPort(new Port(pip.To));
if ((inport | outport) && pip.To.Contains('_'))
{
NetPin pin = null;
if (inport)
{
pin = new NetInpin();
}
else
{
pin = new NetOutpin();
}
string[] atoms = pip.To.Split('_');
pin.SlicePort = atoms[1];
if (netlistContainer.Instances.Any(i => i.SliceName.Equals(s.SliceName)))
{
// there should be only one instance on the slice
XDLInstance inst = (XDLInstance)netlistContainer.Instances.First(i => i.SliceName.Equals(s.SliceName));
pin.InstanceName = inst.Name;
}
else
{
pin.InstanceName = s.SliceName;
}
bool pinExistsAlready = n.NetPins.FirstOrDefault(np => np.InstanceName.Equals(pin.InstanceName) && np.SlicePort.Equals(pin.SlicePort)) != null;
if (!pinExistsAlready)
{
n.Add(pin);
}
}
}
}
}
}
private Dictionary <string, Net> FindNetsToConsiderForFusing(NetlistContainer netlistContainer)
{
Dictionary <string, Net> netsToConsiderForFusing = new Dictionary <string, Net>();
foreach (Net other in netlistContainer.Nets.Where(n => n.OutpinCount == 0 && n.PipCount > 0))
{
netsToConsiderForFusing.Add(other.Name, other);
}
return(netsToConsiderForFusing);
}
private void Print(string output)
{
if (m_firstPrint)
{
m_firstPrint = false;
NetlistContainer nlc = GetNetlistContainer();
OutputManager.WriteOutput("Report for " + nlc.Name);
}
OutputManager.WriteOutput(output);
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer netlistContainer = GetNetlistContainer();
XDLNet net = (XDLNet )netlistContainer.GetNet(Netname);
Regex filter = new Regex(PipRegexp, RegexOptions.Compiled);
net.Remove(pip => filter.IsMatch(pip.ToString()));
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
Regex netFilter = new Regex(NetNameRegexp, RegexOptions.Compiled);
foreach (XDLNet netToUnrotue in netlistContainer.Nets.Where(n => netFilter.IsMatch(n.Name) && !n.ReadOnly))
{
netToUnrotue.ClearPips(true);
}
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
Regex netFilter = new Regex(NetNameRegexp, RegexOptions.Compiled);
// output to be removed nets for later writing them to file
foreach (XDLNet netToRemove in netlistContainer.Nets.Where(n => netFilter.IsMatch(n.Name)))
{
OutputManager.WriteOutput(netToRemove.ToString());
}
}
protected override void DoCommandAction()
{
NetlistContainer nlc = GetNetlistContainer();
Net net = nlc.Nets.FirstOrDefault(n => n.Name.Equals(NetName));
if (net == null)
{
throw new ArgumentException("Net " + NetName + " not found");
}
OutputManager.WriteOutput(net.Name + ":");
OutputManager.WriteOutput(net.ToString());
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
Slice anchor = FPGA.FPGA.Instance.GetSlice(SliceName);
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
if (anchor == null)
{
throw new ArgumentException("Can not find Slice " + SliceName);
}
if (AutoClearModuleSlot)
{
AutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor.ContainingTile, 1));
}
LibElemInst instantiation = new LibElemInst();
instantiation.AnchorLocation = anchor.ContainingTile.Location;
instantiation.InstanceName = Hierarchy + InstanceName;
instantiation.LibraryElementName = LibraryElementName;
instantiation.SliceNumber = anchor.ContainingTile.GetSliceNumberByName(SliceName);
instantiation.SliceName = SliceName;
LibraryElementInstanceManager.Instance.Add(instantiation);
// mark source as blocked
ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking();
markSrc.AnchorLocation = anchor.ContainingTile.Location;
markSrc.LibraryElementName = LibraryElementName;
CommandExecuter.Instance.Execute(markSrc);
SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation();
saveCmd.AddDesignConfig = false;
saveCmd.InsertPrefix = true;
saveCmd.InstanceName = InstanceName;
saveCmd.NetlistContainerName = NetlistContainerName;
CommandExecuter.Instance.Execute(saveCmd);
if (AutoFuse)
{
FuseNets fuseCmd = new FuseNets();
fuseCmd.NetlistContainerName = NetlistContainerName;
fuseCmd.Mute = Mute;
fuseCmd.Profile = Profile;
fuseCmd.PrintProgress = PrintProgress;
CommandExecuter.Instance.Execute(fuseCmd);
}
}
protected override void DoCommandAction()
{
int slicesMax = 0;
int dspMax = 0;
int bramMax = 0;
foreach (string fileName in Files.Where(s => !string.IsNullOrEmpty(s)))
{
int slices = 0;
int dsp = 0;
int bram = 0;
// read file
DesignParser parser = DesignParser.CreateDesignParser(fileName);
// into design
NetlistContainer inContainer = new NetlistContainer();
parser.ParseDesign(inContainer, this);
foreach (Instance inst in inContainer.Instances)
{
if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.CLB))
{
slices++;
}
if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.DSP))
{
dsp++;
}
if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.BRAM))
{
bram++;
}
}
if (slices > slicesMax)
{
slicesMax = slices;
}
if (dsp > dspMax)
{
dspMax = dsp;
}
if (bram > bramMax)
{
bramMax = bram;
}
// TODO chains erkennen
}
// two slices per CLB
OutputManager.WriteOutput("CLBs: " + slicesMax / 2 + " DSPs: " + dspMax + " BRAMs: " + bramMax);
}
protected override void DoCommandAction()
{
NetlistContainer nlc = GetNetlistContainer();
int instIdentifierWidth = (int)Math.Ceiling(Math.Log((double)nlc.InstanceCount, (double)2.0d));
int netIdentifierWidth = (int)Math.Ceiling(Math.Log((double)nlc.NetCount, (double)2.0d));
Dictionary <string, string> instanceReplacements = SimplifyInstanceIdentifier(nlc);
// restart with nets
m_identifier = 0;
SimplifyNetIdentifier(nlc, instanceReplacements);
}
protected override void DoCommandAction()
{
NetlistContainer nlc = GetNetlistContainer();
// find inpins/outpins which reside on unknown primitives
int netCount = 0;
foreach (XDLNet net in nlc.Nets)
{
ProgressInfo.Progress = (int)((double)(netCount++) / (double)nlc.NetCount * 100);
net.RemoveAllPinStatements(np => !nlc.Instances.Any(i => i.SliceName.Equals(np.InstanceName)));
}
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
Regex netFilter = new Regex(NetNameRegexp, RegexOptions.Compiled);
// output to be removed nets for later writing them to file
foreach (XDLNet net in netlistContainer.Nets.Where(n => netFilter.IsMatch(n.Name)))
{
net.ReadOnly = true;
OutputManager.WriteOutput("Setting write protection for net " + net.Name);
}
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
Regex filter = new Regex(InstanceNameRegexp, RegexOptions.Compiled);
// output to be removed nets for later writing them to file
foreach (Instance inst in netlistContainer.Instances.Where(n => filter.IsMatch(n.Name)))
{
OutputManager.WriteOutput(inst.ToString());
}
netlistContainer.Remove(new Predicate <Instance>(n => filter.IsMatch(n.Name)));
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
// do not store addSlice in constructor already!
m_addedSlice = FPGA.FPGA.Instance.Current.Slices[SliceNumber];
/*
* if (netlistContainer.HasSlice(this.m_addedSlice))
* {
* this.OutputManager.WriteOutput("Overwriting slice " + this.m_addedSlice + " in macro " + netlistContainer);
* }*/
netlistContainer.Add(m_addedSlice);
}
protected override void DoCommandAction()
{
NetlistContainer m = GetNetlistContainer();
// build mapping: Location -> XDLNet
Dictionary <string, Dictionary <string, XDLNet> > netConflicts = new Dictionary <string, Dictionary <string, XDLNet> >();
Dictionary <string, Dictionary <string, XDLPip> > pipConflicts = new Dictionary <string, Dictionary <string, XDLPip> >();
foreach (XDLNet n in m.Nets)
{
foreach (XDLPip pip in n.Pips)
{
if (!pip.Operator.Equals("->"))
{
continue;
}
if (!netConflicts.ContainsKey(pip.Location))
{
netConflicts.Add(pip.Location, new Dictionary <string, XDLNet>());
pipConflicts.Add(pip.Location, new Dictionary <string, XDLPip>());
}
// to
if (!netConflicts[pip.Location].ContainsKey(pip.To))
{
netConflicts[pip.Location].Add(pip.To, n);
pipConflicts[pip.Location].Add(pip.To, pip);
}
else
{
XDLNet conflictingNet = netConflicts[pip.Location][pip.To];
XDLPip conflictingPip = pipConflicts[pip.Location][pip.To];
string conflict = " in " + pip.ToString() + " and " + conflictingPip;
if (n.Name.Equals(conflictingNet.Name))
{
OutputManager.WriteOutput("Detected driver conflift in net " + n.Name + conflict);
}
else
{
OutputManager.WriteOutput("Detected driver conflift between nets " + n.Name + " and " + netConflicts[pip.Location][pip.To].Name + conflict);
}
}
}
}
}
protected override void DoCommandAction()
{
NetlistContainer nlc = GetNetlistContainer();
OutputManager.WriteOutput("Name: " + nlc.Name);
OutputManager.WriteOutput("Instances: " + nlc.InstanceCount);
OutputManager.WriteOutput("Nets: " + nlc.Nets.Count());
if (nlc.NetCount > 0)
{
OutputManager.WriteOutput("Average pip count per net: " + nlc.Nets.Average(n => n.PipCount));
OutputManager.WriteOutput("Minimal pip count: " + nlc.Nets.Min(n => n.PipCount));
OutputManager.WriteOutput("Maximal pip count: " + nlc.Nets.Max(n => n.PipCount));
OutputManager.WriteOutput("-----------------------------------------");
IEnumerable <Net> netsWithoutOutpin = nlc.Nets.Where(n => n.OutpinCount == 0);
OutputManager.WriteOutput("Nets without Outpin: " + netsWithoutOutpin.Count());
PrintHits(netsWithoutOutpin);
OutputManager.WriteOutput("-----------------------------------------");
IEnumerable <Net> netsWithoutOutpinWithMoreThanOnePip = nlc.Nets.Where(n => n.OutpinCount == 0 && n.PipCount > 0);
OutputManager.WriteOutput("Nets without Outpin and more than one pip: " + netsWithoutOutpinWithMoreThanOnePip.Count());
PrintHits(netsWithoutOutpinWithMoreThanOnePip);
OutputManager.WriteOutput("-----------------------------------------");
IEnumerable <Net> netsWithoutIntpin = nlc.Nets.Where(n => n.InpinCount == 0);
OutputManager.WriteOutput("Nets without Inpin: " + netsWithoutIntpin.Count());
PrintHits(netsWithoutIntpin);
OutputManager.WriteOutput("-----------------------------------------");
IEnumerable <Net> singelInpinNets = nlc.Nets.Where(n => n.InpinCount == 1 && n.OutpinCount == 0 && n.PipCount == 0);
OutputManager.WriteOutput("Single inpin nets (dummy nets): " + singelInpinNets.Count());
PrintHits(singelInpinNets);
}
if (PrintAntennas)
{
PrintAntennas printAntennasCmd = new PrintAntennas();
printAntennasCmd.NetlistContainerName = NetlistContainerName;
// consider all nets
printAntennasCmd.PositiveFilter = ".*";
printAntennasCmd.NegativeFilter = "";
CommandExecuter.Instance.Execute(printAntennasCmd);
}
}
private NetlistContainer ReadBlocker(string blockerFileName)
{
NetlistContainer blocker = new NetlistContainer("blocker");
// read file
XDLDesignParser parser = new XDLDesignParser(blockerFileName);
// into design
try
{
parser.ParseDesign(blocker, this);
}
catch (Exception e)
{
throw new ArgumentException("Error during parsing the design " + blockerFileName + ": " + e.Message + ". Are you trying to open the design on the correct device?");
}
return(blocker);
}
private void RelocateNetsForTCL(LibraryElement libElement, Tile anchorCLB, NetlistContainer netlistContainer)
{
foreach (TCLNet net in libElement.Containter.Nets)
{
TCLNet relocatedNet = TCLNet.Relocate(net, libElement, anchorCLB);
relocatedNet.Name = InstanceName + relocatedNet.Name;
// relocate NetPins
foreach (NetPin pin in relocatedNet.NetPins)
{
if (InsertPrefix)
{
pin.InstanceName = InstanceName + pin.InstanceName;
}
}
netlistContainer.Add(relocatedNet);
}
}
