private LibraryElement GetFF(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort)
{
LibraryElement el = new LibraryElement();
el.SliceNumber = SliceNumber;
el.Name = belName;
el.PrimitiveName = BELType;
el.BEL = belName;
el.LoadCommand = ToString();
el.Containter = new NetlistContainer();
el.VHDLGenericMap = "generic map ( INIT => '0' )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// Q output
XDLPort q = new XDLPort();
q.Direction = FPGATypes.PortDirection.Out;
q.ExternalName = "Q";
q.InstanceName = "unknown";
q.SlicePort = "unknown";
el.Containter.Add(q);
List <string> inputs = new List <string>();
inputs.Add("D");
inputs.Add("C");
inputs.Add("CE");
inputs.Add("R");
foreach (string i in inputs)
{
XDLPort p = new XDLPort();
p.Direction = FPGATypes.PortDirection.In;
p.ExternalName = i;
p.InstanceName = "unknown";
p.SlicePort = "unknown";
p.ConstantValuePort = false;
el.Containter.Add(p);
}
;
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
foreach (string stopOverPortName in StopOverPorts)
{
el.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(el);
}
private LibraryElement GetLUT(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort, string initValue)
{
int lutSize = 6;
LibraryElement el = new LibraryElement();
el.SliceNumber = SliceNumber;
el.Name = belName;
el.PrimitiveName = BELType;
el.BEL = belName;
el.LoadCommand = ToString();
el.Containter = new NetlistContainer();
el.VHDLGenericMap = "generic map ( INIT => X\"" + initValue + "\" )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// one output per LUT
XDLPort outPort = new XDLPort();
outPort.Direction = FPGATypes.PortDirection.Out;
outPort.ExternalName = "O";
outPort.InstanceName = "unknown";
outPort.SlicePort = "unknown";
el.Containter.Add(outPort);
// six inputs I=..I5
for (int i = 0; i < lutSize; i++)
{
AddXDLPort(el, "I", i, FPGATypes.PortDirection.In, makeInputsConstant);
}
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
List <string> lutPortNames = new List <string>();
// see LUTRouting tab
for (int i = 1; i <= lutSize; i++)
{
lutPortNames.Add(inputPortPrefix + i);
}
foreach (string stopOverPortName in StopOverPorts)
{
el.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(el);
}
private LibraryElement GetBEL(BELInfo info)
{
LibraryElement element = new LibraryElement
{
SliceNumber = SliceNumber,
Name = info.belName,
PrimitiveName = BELType,
BEL = info.belName,
LoadCommand = ToString(),
Containter = new XDLModule(),
VHDLGenericMap = info.type.VHDLGenericMap,
VivadoConnectionPrimitive = true
};
// Outputs
foreach (string output in info.type.outputNames)
{
element.Containter.Add(MakeXDLPort(output, FPGATypes.PortDirection.Out));
}
// Inputs
foreach (string input in info.type.inputNames)
{
element.Containter.Add(MakeXDLPort(input, FPGATypes.PortDirection.In, info.type.inputsConstantValue));
}
// Get first encountered clb ?!
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
if (info.traverseBackwards)
{
TraverseBackwards(element, clb, interconnect, info);
}
foreach (string stopOverPortName in StopOverPorts)
{
element.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(element);
}
private void TraverseBackwards(LibraryElement element, Tile clb, Tile interconnect, BELInfo info)
{
List <string> lutPortNames = new List <string>();
// see LUTRouting tab
for (int i = 1; i <= info.type.inputNames.Count; i++)
{
lutPortNames.Add(info.inputPortPrefix + i);
}
foreach (string s in lutPortNames)
{
// travers backwards into INT
foreach (Tuple <Port, Port> t in clb.SwitchMatrix.GetAllArcs().Where(a => a.Item2.Name.EndsWith(s)))
{
element.AddPortToBlock(clb, t.Item1);
element.AddPortToBlock(clb, t.Item2);
if (interconnect.WireList == null)
{
OutputManager.WriteWarning("No wire list found on " + interconnect.Location);
}
else
{
foreach (Wire w in interconnect.WireList.Where(w => w.PipOnOtherTile.Equals(t.Item1.Name)))
{
element.AddPortToBlock(interconnect, new FPGA.Port(w.LocalPip));
}
}
}
}
// we always need to exclude the port from the LUT output from blocking
// assuming name
foreach (Tuple <Port, Port> t in clb.SwitchMatrix.GetAllArcs().Where(a => a.Item1.Name.EndsWith(info.outputPort)))
{
// no realy neccessary
element.AddPortToBlock(clb, t.Item1);
element.AddPortToBlock(clb, t.Item2);
foreach (Wire w in clb.WireList.Where(w => w.LocalPip.Equals(t.Item2.Name)))
{
element.AddPortToBlock(interconnect, new Port(w.PipOnOtherTile));
}
}
}
private void DeriveBlockingData(LibraryElement libElement)
{
////////////////////////////
// find LOGICIN and LOGICOUT
foreach (XDLPort xdlPort in ((XDLContainer)libElement.Containter).Ports)
{
XDLInstance inst = (XDLInstance)libElement.Containter.GetInstanceByName(xdlPort.InstanceName);
Tile clb = FPGA.FPGA.Instance.GetTile(inst.Location);
Tile interconnectTile = FPGATypes.GetInterconnectTile(clb);
Slice slice = clb.GetSliceByName(inst.SliceName);
// true: in, false: out (no needed)
Dictionary <uint, bool> portMapping = new Dictionary <uint, bool>();
foreach (Port inPort in slice.PortMapping.GetPorts(FPGATypes.PortDirection.In))
{
portMapping.Add(inPort.NameKey, true);
}
// 1 store all ports we need to connect the switchmatrx with macro in ports
foreach (Tuple <Port, Port> intArc in interconnectTile.SwitchMatrix.GetAllArcs())
{
bool portFound = false;
// find the arc that is driven by the xdlPort && make sure that we get the correct slice
foreach (Location loc in Navigator.GetDestinations(interconnectTile, intArc.Item2).Where(l => l.Tile.Location.Equals(clb.Location)))
{
foreach (Port clbPort in clb.SwitchMatrix.GetDrivenPorts(loc.Pip).Where(drivenPort => portMapping.ContainsKey(drivenPort.NameKey) && drivenPort.Name.EndsWith(xdlPort.SlicePort)))
{
libElement.AddPortToBlock(interconnectTile, intArc.Item2);
portFound = true;
break;
}
if (portFound)
{
break;
}
}
}
// 2 store all ports we need to connect the macro out ports to the switch matrix (LOGICOUT\d+)
// // find the arc that is driven by the xdlPort && make sure that we get the correct slice
foreach (Tuple <Port, Port> arc in clb.SwitchMatrix.GetAllArcs().Where(a => slice.PortMapping.IsSliceOutPort(a.Item1) && a.Item1.Name.EndsWith(xdlPort.SlicePort)))
{
foreach (Location loc in Navigator.GetDestinations(clb, arc.Item2))
{
libElement.AddPortToBlock(loc.Tile, loc.Pip);
}
}
}
////////////////////////////
// extract begin pips to block
foreach (XDLNet net in libElement.Containter.Nets)
{
foreach (XDLPip pip in net.Pips)
{
libElement.AddPortToBlock(FPGA.FPGA.Instance.GetTile(pip.Location), new Port(pip.From));
libElement.AddPortToBlock(FPGA.FPGA.Instance.GetTile(pip.Location), new Port(pip.To));
}
}
// sideeffect, trigger calculation of slice number to reuse this macro on other devices
foreach (XDLInstance inst in libElement.Containter.Instances)
{
inst.DeriveTileKeyAndSliceNumber();
}
// CLB anchor
if (((XDLContainer)libElement.Containter).ExplicitAnchorFound)
{
if (((XDLContainer)libElement.Containter).HasInstanceByName(((XDLContainer)libElement.Containter).Anchor))
{
XDLInstance anchorInst = (XDLInstance)libElement.Containter.GetInstanceByName(((XDLContainer)libElement.Containter).Anchor);
libElement.ResourceShape.Anchor.AnchorLocationX = anchorInst.LocationX;
libElement.ResourceShape.Anchor.AnchorLocationY = anchorInst.LocationY;
libElement.ResourceShape.Anchor.AnchorSliceName = anchorInst.SliceName;
libElement.ResourceShape.Anchor.AnchorSliceNumber = anchorInst.SliceNumber;
libElement.ResourceShape.Anchor.AnchorTileLocation = anchorInst.Location;
}
else
{
Slice anchorSlice = FPGA.FPGA.Instance.GetSlice(((XDLContainer)libElement.Containter).Anchor);
libElement.ResourceShape.Anchor.AnchorLocationX = anchorSlice.ContainingTile.LocationX;
libElement.ResourceShape.Anchor.AnchorLocationY = anchorSlice.ContainingTile.LocationY;
libElement.ResourceShape.Anchor.AnchorSliceName = anchorSlice.SliceName;
libElement.ResourceShape.Anchor.AnchorSliceNumber = 0; // see CutOffFromDesign
libElement.ResourceShape.Anchor.AnchorTileLocation = anchorSlice.ContainingTile.Location;
}
}
else
{
// TODO der Slot muss ausgewaehlt sein!
SetResourceShapeInfo setCmd = new SetResourceShapeInfo();
setCmd.LibraryElementName = libElement.Name;
CommandExecuter.Instance.Execute(setCmd);
}
}
