/// <summary>
/// copy and relocate the net
/// </summary>
/// <param name="other"></param>
public static TCLNet Relocate(TCLNet other,LibraryElement libElement,Tile anchor)
{
TCLNet copiedNet = new TCLNet(other.Name);
copiedNet.RoutingTree = new TCLRoutingTree(other.RoutingTree);
foreach (TCLRoutingTreeNode node in copiedNet.RoutingTree.GetAllRoutingNodes().Where(n => n.Tile != null))
{
string targetLocation = "";
bool success = libElement.GetTargetLocation(node.Tile.Location, anchor, out targetLocation);
Tile targetTile = FPGA.FPGA.Instance.GetTile(targetLocation);
node.Tile = targetTile;
}
copiedNet.m_footerComment.Append(other.FooterComment);
copiedNet.Properties = new TCLProperties(other.Properties);
copiedNet.m_netPins = new List <NetPin>();
foreach (NetPin pin in other.NetPins)
{
NetPin copiedPin = NetPin.Copy(pin);
copiedNet.m_netPins.Add(copiedPin);
string targetLocation = "";
bool success = libElement.GetTargetLocation(pin.TileName, anchor, out targetLocation);
Tile targetTile = FPGA.FPGA.Instance.GetTile(targetLocation);
pin.TileName = targetTile.Location;
}
copiedNet.IsBlockerNet = other.IsBlockerNet;
copiedNet.NodeNet = other.NodeNet;
if (other.OutpinInstance != null)
{
copiedNet.OutpinInstance = new TCLInstance((TCLInstance)other.OutpinInstance);
}
return(copiedNet);
}
private void RelocateNetsForXDL(LibraryElement libElement, Tile anchorCLB, XDLContainer netlistContainer)
{
foreach (XDLNet net in libElement.Containter.Nets)
{
// insert instance prefix
XDLNet relocatedNet = new XDLNet(InstanceName + net.Name);
relocatedNet.HeaderExtension = net.HeaderExtension;
foreach (NetPin pin in net.NetPins)
{
NetPin copy = NetPin.Copy(pin);
if (InsertPrefix)
{
// insert instance prefix
// remove greedy between double quotes
string oldInstanceName = pin.InstanceName;
string newInstanceName = "\"" + InstanceName + Regex.Replace(oldInstanceName, "\"", "") + "\"";
//xdlCode = Regex.Replace(xdlCode, oldInstanceName, newInstanceName);
copy.InstanceName = newInstanceName;
copy.InstanceName = copy.InstanceName.Replace("\"", "");
}
relocatedNet.Add(copy);
}
//foreach (NetSegment seg in originalNet.GetAllSegments())
foreach (XDLPip pip in net.Pips)
{
string targetLocation;
bool success = libElement.GetTargetLocation(pip.Location, anchorCLB, out targetLocation);
Tile targetTile = null;
if (FPGA.FPGA.Instance.Contains(targetLocation))
{
targetTile = FPGA.FPGA.Instance.GetTile(targetLocation);
}
else
{
throw new ArgumentException("Error during relocation of pip " + pip + " to " + targetLocation);
}
XDLPip relocatedSegment = null;
if (targetTile.SwitchMatrix.Contains(pip.From, pip.To))
{
// we do not need to transform identifiers
relocatedSegment = new XDLPip(targetTile.Location, pip.From, pip.Operator, pip.To);
}
else
{
// naming fun
relocatedSegment = FPGATypes.RelocatePip(targetTile, pip, relocatedNet);
}
if (relocatedSegment == null)
{
throw new ArgumentException("Could not relocate " + pip.ToString() + " to tile " + targetLocation);
}
if (!targetTile.SwitchMatrix.Contains(relocatedSegment.From, relocatedSegment.To))
{
throw new ArgumentException("Could not relocate " + pip.ToString() + " to tile " + targetLocation);
}
relocatedNet.Add(relocatedSegment);
}
if (netlistContainer.Nets.Any(n => n.Name.Equals(relocatedNet.Name)))
{
throw new ArgumentException("A net named " + relocatedNet.Name + " is alredy inserted to netlist " + netlistContainer.Name + ". Did you try to join two instances of the same macro in one?");
}
netlistContainer.Add(relocatedNet);
}
}
protected void AutoClearModuleSlotBeforeInstantiation(LibraryElement libraryElement, IEnumerable <Tile> upperLeftAnchors, int progressStart = 0, int progressShare = 100)
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
if (libraryElement.ResourceShape == null)
{
throw new ArgumentException("Library element " + libraryElement.Name + " does not provide any module shape information");
}
NetlistContainer nlc = GetNetlistContainer();
Dictionary <string, bool> targetLocations = new Dictionary <string, bool>();
foreach (string originalTileIdnetifier in libraryElement.ResourceShape.GetContainedTileIdentifier().Where(s => !s.StartsWith("NULL")))
{
bool validTargetTileFound = false;
foreach (Tile anchor in upperLeftAnchors)
{
string targetLocation = "";
bool success = libraryElement.GetTargetLocation(originalTileIdnetifier, anchor, out targetLocation);
if (!targetLocations.ContainsKey(targetLocation))
{
targetLocations.Add(targetLocation, true);
}
if (success)
{
validTargetTileFound = true;
}
}
if (!validTargetTileFound)
{
OutputManager.WriteWarning("Could not relocate " + originalTileIdnetifier);
}
}
int netsDone = 0;
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
foreach (XDLNet net in nlc.Nets.Where(n => !n.ReadOnly))
{
ProgressInfo.Progress = progressStart + (int)((double)netsDone++ / (double)nlc.NetCount * progressShare);
RemovePipsFromNet((XDLContainer)nlc, targetLocations, net);
}
// remove all nets that are now empty
nlc.Remove(new Predicate <Net>(n => n.PipCount == 0 && n.InpinCount == 0 && n.OutpinCount == 0));
break;
case FPGATypes.BackendType.Vivado:
foreach (TCLNet net in nlc.Nets)
{
ProgressInfo.Progress = (int)((double)netsDone++ / (double)nlc.NetCount * 100);
// only flatten in we will really remove something, otherwise keep the tree structure to save processing later
if (net.RoutingTree.GetAllRoutingNodes().Any(n => !n.VirtualNode && TileSelectionManager.Instance.IsSelected(n.Tile)))
{
net.FlattenNet();
net.Remove(node => !node.VirtualNode && TileSelectionManager.Instance.IsSelected(node.Tile));
net.Remove(new Predicate <NetPin>(np => TileSelectionManager.Instance.IsSelected(np.TileName)));
// remove the outpins instance if it is selected
if (net.OutpinInstance != null)
{
if (TileSelectionManager.Instance.IsSelected(net.OutpinInstance.Location))
{
net.OutpinInstance = null;
}
}
}
}
break;
}
// handle instances equally (XDL and TCL), only nets differ
nlc.Remove(inst => targetLocations.ContainsKey(inst.Location));
}
