public override bool Configure(NES.EDetectionOrigin origin)
{
//configure
switch (Cart.board_type)
{
case "MAPPER176":
break;
default:
return false;
}
prg_bank_mask_8k = (Cart.prg_size / 8) - 1;
chr_bank_mask_8k = (Cart.chr_size / 8) - 1;
mirror = 0;
SyncMirror();
sbw = 0;
prg_banks_8k[0] = 0;
prg_banks_8k[1] = 1;
prg_banks_8k[2] = 62;
prg_banks_8k[3] = 63;
ApplyMemoryMapMask(prg_bank_mask_8k,prg_banks_8k);
chr_banks_8k[0] = 0;
ApplyMemoryMapMask(chr_bank_mask_8k, chr_banks_8k);
return true;
}
public override void WriteEXP(int addr, byte value)
{
switch (addr)
{
case 0x1000: //0x5000
break;
case 0x1001: //0x5001
if (sbw) SetPrg32k(value);
break;
case 0x1010: //0x5010
if (value == 0x24) sbw = 1;
break;
case 0x1011: //0x5011
if (sbw) SetPrg32k(value >> 1);
break;
case 0x1FF1: //0x5FF1
SetPrg32k(value>>1);
break;
case 0x1FF2: //0x5FF2
chr_banks_8k[0] = (byte)value;
ApplyMemoryMapMask(chr_bank_mask_8k, chr_banks_8k);
break;
}
}
byte read_2002()
{
//once we thought we clear latches here, but that caused midframe glitches.
//i think we should only reset the state machine for 2005/2006
//ppur.clear_latches();
byte ret = peek_2002();
vtoggle = false;
Reg2002_vblank_active = 0;
Reg2002_vblank_active_pending = false;
return ret;
}
void clear_2002()
{
Reg2002_objhit = Reg2002_objoverflow = 0;
Reg2002_vblank_clear_pending = true;
}
void regs_reset()
{
//TODO - would like to reconstitute the entire PPU instead of all this..
reg_2000 = new Reg_2000(this);
reg_2001 = new Reg_2001();
ppur = new PPUREGS(this);
Reg2002_objoverflow = false;
Reg2002_objhit = false;
Reg2002_vblank_active = false;
PPUGenLatch = 0;
reg_2003 = 0;
vtoggle = false;
VRAMBuffer = 0;
}