public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
const uint baud = 115200;
Sequential handler = () =>
{
FPGA.Optimizations.AddOptimizer <TestOptimizer>();
float f1 = 0, f2 = 1.234f;
bool internalTXD = true;
// hardlink from register to output signal, it has to hold its value
FPGA.Config.Link(internalTXD, TXD);
while (true)
{
UART.ReadFloat(baud, RXD, out f1);
UART.RegisteredWriteFloat(baud, f1, out internalTXD);
//UART.RegisteredWriteFloat(baud, f2, out internalTXD);
}
};
FPGA.Config.OnStartup(handler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD)
{
const int baud = 115200;
bool internalTXD = true;
FPGA.Config.Link(internalTXD, TXD);
FPGA.Signal <bool> handler0 = false, handler1 = false;
float res0 = 0, res1 = 0;
FPGA.Config.Suppress("W0003", handler0, handler1, res0, res1);
Sequential handler = () =>
{
uint idx = FPGA.Config.InstanceId();
FPU.FPUScope();
float op1, op2, res = 0;
UART.ReadFloat(baud, RXD, out op1);
UART.ReadFloat(baud, RXD, out op2);
FloatControllersOps.TestHandler(op1, op2, 0, out res);
// TODO: this is constant expression, should remove branch comletely
if (idx == 0)
{
res0 = res;
handler0 = true;
}
else
{
res1 = res;
handler1 = true;
}
};
FPGA.Config.OnStartup(handler, 2);
// expect to be completed at exactly the same time as they should not share FPU
Func <bool> trigger = () => handler0 && handler1;
Sequential onTigger = () =>
{
UART.RegisteredWriteFloat(baud, res0, out internalTXD);
UART.RegisteredWriteFloat(baud, res1, out internalTXD);
};
FPGA.Config.OnSignal(trigger, onTigger);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
const int baud = 115200;
uint clockCounter = 0;
Diag.ClockCounter(clockCounter);
bool internalTXD = true;
FPGA.Config.Link(internalTXD, TXD);
byte testOp;
float op1, op2, res = 0;
Sequential handler = () =>
{
FPU.FPUScope();
while (true)
{
uint start = 0, end = 0;
res = 0;
UART.Read(baud, RXD, out testOp);
UART.ReadFloat(baud, RXD, out op1);
UART.ReadFloat(baud, RXD, out op2);
switch ((FPUTimingType)testOp)
{
case FPUTimingType.Add:
start = clockCounter;
res = op1 + op2;
end = clockCounter;
break;
case FPUTimingType.Sub:
start = clockCounter;
res = op1 - op2;
end = clockCounter;
break;
case FPUTimingType.Mul:
start = clockCounter;
res = op1 * op2;
end = clockCounter;
break;
case FPUTimingType.Div:
start = clockCounter;
res = op1 / op2;
end = clockCounter;
break;
default:
start = clockCounter;
end = clockCounter;
break;
}
UART.RegisteredWriteFloat(baud, res, out internalTXD);
UART.RegisteredWriteUnsigned32(baud, end - start, out internalTXD);
}
};
FPGA.Config.OnStartup(handler);
}
