public void SetUp() { Instruction instr1 = new AddInstruction(2, 3, 4); Instruction instr2 = new LuiInstruction(5, 0xFFFF); Instruction[] instructions = { instr1, instr2 }; target = new InstructionMemory(instructions); }
public void SetInstruction_ValidIndex() { target = new InstructionMemory(8); Instruction instr = new AddInstruction(1, 1, 2); target[4] = 0x00220820; //Assert.AreEqual(instr, target.GetInstruction(4)); }
// constructor public Processor(int _id, int n_cores, int isntrmem_size, int shrmem_size) { id = _id; cores = new Core[n_cores]; for (int i = 0; i < cores.Length; i++) { cores[i] = new Core(i, this); } isntrmem = new InstructionMemory(isntrmem_size); shrmem = new SharedMemory(shrmem_size, this); dir = new DirectoryProc(shrmem_size, numCaches); }
//[Ignore("TEST NOT YET NEEDED")] public void TestInitInstructionMemory() { uint[] instructions = new uint[] { 0x201d0f3c, 0x3c08ffff, 0x3508ffff, 0x2009ffff, 0x1509001b, 0x00084600, 0x3508f000, 0x00084203, 0x00084102, 0x340a0003, 0x01495022, 0x01484004, 0x010a582a, 0x010a582b, 0x20080005, 0x2d0b000a, 0x2d0b0004, 0x2008fffb, 0x2d0b0005, 0x3c0b1010, 0x356b1010, 0x3c0c0101, 0x218c1010, 0x016c6824, 0x016c6825, 0x016c6826, 0x016c6827, 0x8c040004, 0x20840002, 0x2484fffe, 0x0c000021, 0xac020000, 0x08000020, 0x23bdfff8, 0xafbf0004, 0xafa40000, 0x28880002, 0x11000002, 0x00041020, 0x0800002e, 0x2084ffff, 0x0c000021, 0x8fa40000, 0x00441020, 0x00441020, 0x2042ffff, 0x8fbf0004, 0x23bd0008, 0x03e00008 }; InstructionFactory instrFact = new InstructionFactory(); Instruction[] instrs = new Instruction[instructions.Length]; int i = 0; foreach (uint instr in instructions) { instrs[i] = instrFact.CreateInstruction(instr); i++; } target = new InstructionMemory(instrs); uint pc = 0; var dataMem = new DataMemory(10000); var map = new MappedMemoryUnit(dataMem, 0); var unitList = new List <MappedMemoryUnit> { map }; var dataMemory = new MemoryMapper(unitList); var registers = new Registers(); int icount = 0; uint a = 99; dataMemory[4] = a; while (pc < instructions.Length * 4 && icount < 1000000) { //Console.WriteLine($"{pc:X8}: {target[pc]}"); target.GetInstruction(pc).Execute(ref pc, dataMemory, registers); icount++; } Console.WriteLine(dataMemory[0]); Assert.AreEqual(a * a, dataMemory[0]); }
static CPU() { RegisterFile = new GenericMemory(16); DataMemory = new GenericMemory(16); PC = new ProgramCounter(); Instructions = new InstructionMemory(); IsReady = false; _clockCycle = 0; _isStalled = false; InstructionQueue = new Queue<Instruction>(); AwaitingRegisters = new HashSet<int>(); ForwardedRegisters = new Dictionary<int, int>(); }
static CPU() { RegisterFile = new GenericMemory(16); DataMemory = new GenericMemory(16); PC = new ProgramCounter(); Instructions = new InstructionMemory(); IsReady = false; _clockCycle = 0; _isStalled = false; InstructionQueue = new Queue <Instruction>(); AwaitingRegisters = new HashSet <int>(); ForwardedRegisters = new Dictionary <int, int>(); }
public bool Step() { int PC = ScalarRegisterFile[31]; RTInstruction ins; if (!cache.TryGetValue(PC, out ins)) { ins = (RTInstruction)decoder.Decode(InstructionMemory.Read(PC)); cache[PC] = ins; } LastInstruction = ins.ToString(); if (ins is fin) { return(true); } ScalarRegisterFile[31] += 4; ins.Process(VectorRegisterFile, ScalarRegisterFile, DataMemory, IC); return(false); }
public void SetUp() { uint[] instructions = new uint[] { 0x201d0f3c, 0x3c08ffff, 0x3508ffff, 0x2009ffff, 0x1509001b, 0x00084600, 0x3508f000, 0x00084203, 0x00084102, 0x340a0003, 0x01495022, 0x01484004, 0x010a582a, 0x010a582b, 0x20080005, 0x2d0b000a, 0x2d0b0004, 0x2008fffb, 0x2d0b0005, 0x3c0b1010, 0x356b1010, 0x3c0c0101, 0x218c1010, 0x016c6824, 0x016c6825, 0x016c6826, 0x016c6827, 0x8c040004, 0x20840002, 0x2484fffe, 0x0c000021, 0xac020000, 0x08F00020, 0x23bdfff8, 0xafbf0004, 0xafa40000, 0x28880002, 0x11000002, 0x00041020, 0x0800002e, 0x2084ffff, 0x0c000021, 0x8fa40000, 0x00441020, 0x00441020, 0x2042ffff, 0x8fbf0004, 0x23bd0008, 0x03e00008 }; InstructionFactory instrFact = new InstructionFactory(); Instruction[] instrs = new Instruction[instructions.Length]; for (int i = 0; i < instructions.Length; i++) { instrs[i] = instrFact.CreateInstruction(instructions[i]); } InstructionMemory instrMem = new InstructionMemory(instrs); var dataMem = new DataMemory(10000); dataMem[4] = 99; var map = new MappedMemoryUnit(dataMem, 0); var unitList = new List <MappedMemoryUnit> { map }; var mem = new MemoryMapper(unitList); memDict = new Dictionary <Type, List <MemoryUnit> >(); memDict.Add(instrMem.GetType(), new List <MemoryUnit> { instrMem }); memDict.Add(mem.GetType(), new List <MemoryUnit> { mem }); target = new Mips(0x0, memDict); }
public void LoadCode(string code) { var rgx = new Regex("[^0-9:\\n]"); var instSplit = rgx.Replace(code, "").Split(); var entry = new string[] { }; foreach (var inst in instSplit) { entry = inst.Split(':'); var instructionCharArray = entry[1].ToCharArray(); Array.Reverse(instructionCharArray); InstructionMemory.Add(uint.Parse(entry[0]), new string(instructionCharArray)); } var lastAddress = uint.Parse(entry[0]); for (var i = 0; i < 4; i++) { lastAddress += 4; InstructionMemory.Add(lastAddress, new string('0', 32)); } InstructionsCount = instSplit.Length; }
public CPU() { _registerFile = new GenericMemory(16); _dataMemory = new GenericMemory(16); _pc = new ProgramCounter(); _instructions = new InstructionMemory(); _stack = new ProcedureStack(); IsReady = false; ClockCycle = 0; _instructionExecution = 0; _isStalled = false; _instructionQueue = new Queue<Instruction>(); _awaitingRegisters = new HashSet<int>(); _forwardedRegisters = new Dictionary<int, int>(); ExecutionRecords = new List<ExecutionRecordList>(); Predictor = new BTB(); _registerFile.Write(0, 0); Instance = this; }