private static bool N(uint uInstr, MilStd1750Disassembler dasm)
{
var n = (ushort)bf4_4.Read(uInstr);
dasm.ops.Add(ImmediateOperand.Word16(n));
return(true);
}
/// <summary>
/// Base relative.
/// </summary>
private static Mutator <MilStd1750Disassembler> br(RegisterStorage reg)
{
var regOp = new RegisterOperand(reg);
return((u, d) =>
{
var disp = bf0_8.Read(u);
d.ops.Add(regOp);
d.ops.Add(ImmediateOperand.Word16((ushort)disp));
return true;
});
}
private static Mutator <MicroMipsDisassembler> Ms(PrimitiveType dt)
{
return((u, d) =>
{
var iBase = (int)baseField.Read(u);
var baseReg = d.arch.GetRegister(iBase);
var offset = offsetField.ReadSigned(u) * dt.Size;
var mop = new IndirectOperand(dt, offset, baseReg);
d.ops.Add(mop);
return true;
});
}
public override TInstr Decode(ulong wInstr, TDasm dasm)
{
TraceDecoder(wInstr);
uint op = bitfield.Read(wInstr);
return(decoders[op].Decode(wInstr, dasm));
}
/// <summary>
/// 8-bit register encoded in 4 bits at bit position 8
/// </summary>
private static bool rb8(uint uInstr, H8Disassembler dasm)
{
var iReg = r8_4.Read(uInstr);
dasm.ops.Add(new RegisterOperand(Registers.Gp8Registers[iReg]));
return(true);
}
private static Mutator <LatticeMico32Disassembler> IsZero(int bitpos, int bitlength)
{
var field = new Bitfield(bitpos, bitlength);
return((u, d) =>
{
var n = field.Read(u);
return n == 0;
});
}
public override X86Instruction Decode(uint op, X86Disassembler disasm)
{
// 62 must be the first byte. The presence of previous
// prefixes is an error (according to Intel manual 2.6, vol 2A.
var ctx = disasm.decodingContext;
if (ctx.F2Prefix |
ctx.F3Prefix |
ctx.IsRegisterExtensionActive() |
ctx.SizeOverridePrefix)
{
return(disasm.CreateInvalidInstruction());
}
// The EVEX prefix consists of a leading 0x62 byte, and three
// packed payload bytes P0, P1, and P2.
//$TODO: this is incomplete: there are many missing flags.
if (!disasm.TryReadByte(out byte p0) ||
!disasm.TryReadByte(out byte p1) ||
!disasm.TryReadByte(out byte p2) ||
p0Reserved.Read(p0) != 0 ||
p1Reserved.Read(p1) != 1)
{
return(disasm.CreateInvalidInstruction());
}
var pp = p1 & 3;
var rxb = p0 >> 5;
var w = p1 >> 7;
var vvvv = p1Vvvv.Read(p1);
ctx.IsVex = true;
ctx.VexRegister = (byte)vvvv;
ctx.VexLong = (op & 4) != 0;
ctx.RegisterExtension.FlagWideValue = w != 0;
ctx.RegisterExtension.FlagTargetModrmRegister = (rxb & 4) == 0;
ctx.RegisterExtension.FlagTargetSIBIndex = (rxb & 2) == 0;
ctx.RegisterExtension.FlagTargetModrmRegOrMem = (rxb & 1) == 0;
ctx.F2Prefix = pp == 3;
ctx.F3Prefix = pp == 2;
ctx.SizeOverridePrefix = pp == 1;
Decoder[] decoders;
switch (pp)
{
case 2: decoders = decoders0F38; break;
case 3: decoders = decoders0F3A; break;
default: decoders = decoders0F; break;
}
if (!disasm.TryReadByte(out byte op2))
{
return(disasm.CreateInvalidInstruction());
}
return(decoders[op2].Decode(op2, disasm));
}
public static Mutator Reg(int n)
{
var regField = new Bitfield(n, 4);
return((u, d) =>
{
var nReg = regField.Read(u);
d.operands.Add(RegOps[nReg]);
return true;
});
}
private static Mutator <OpenRISCDisassembler> Iu(int bitPos, int bitLength)
{
var field = new Bitfield(bitPos, bitLength);
return((u, d) =>
{
var n = field.Read(u);
d.ops.Add(new ImmediateOperand(Constant.Create(d.arch.WordWidth, n)));
return true;
});
}
internal static Mutator <PowerPcDisassembler> u(int pos, int len)
{
var field = new Bitfield(pos, len);
return((u, d) =>
{
var op = new ImmediateOperand(Constant.Byte((byte)field.Read(u)));
d.ops.Add(op);
return true;
});
}
private static Mutator <MCoreDisassembler> Imm(int bitpos, int bitlen)
{
var immField = new Bitfield(bitpos, bitlen);
return((u, d) =>
{
var imm = immField.Read(u);
d.ops.Add(ImmediateOperand.Word32(imm));
return true;
});
}
private static Mutator <MilStd1750Disassembler> Reg(int bitpos)
{
var bitfield = new Bitfield(bitpos, 4);
return((u, d) =>
{
var iReg = bitfield.Read(u);
d.ops.Add(new RegisterOperand(Registers.GpRegs[iReg]));
return true;
});
}
private static Mutator <YmpDisassembler> Imm(PrimitiveType dt, int bitpos, int bitlen, uint nFrom)
{
var bitfield = new Bitfield(bitpos, bitlen);
return((u, d) =>
{
var imm = bitfield.Read(u);
d.ops.Add(new ImmediateOperand(Constant.Create(dt, nFrom - imm)));
return true;
});
}
internal static Mutator <YmpDisassembler> ImmFrom(uint from, PrimitiveType dt, int bitpos, int bitlen)
{
var bitfield = new Bitfield(bitpos, bitlen);
return((u, d) =>
{
var imm = from - bitfield.Read(u);
d.ops.Add(new ImmediateOperand(Constant.Create(dt, imm)));
return true;
});
}
private static Mutator <Cr16cDisassembler> Reg(int bitpos)
{
var regfield = new Bitfield(bitpos, 4);
return((u, d) =>
{
var ireg = regfield.Read(u);
d.ops.Add(new RegisterOperand(Registers.GpRegisters[ireg]));
return true;
});
}
/// <summary>
/// Register.
/// </summary>
private static Mutator <C166Disassembler> R(int bitPos, RegisterStorage [] regs)
{
var regField = new Bitfield(bitPos, 4);
return((u, d) =>
{
var reg = regs[regField.Read(u)];
d.ops.Add(new RegisterOperand(reg));
return true;
});
}
// Rw: 5-bit register identifier from a wide instruction
private static WideMutator<NanoMipsDisassembler> Rw(int pos)
{
var field = new Bitfield(pos, 5);
return (u, d) =>
{
var iReg = (int) field.Read(u);
var reg = d.arch.GetRegister(iReg);
d.ops.Add(new RegisterOperand(reg));
return true;
};
}
// Unsigned immediate
private static Mutator <RiscVDisassembler> Imm(int bitPos1, int length1)
{
var mask = new Bitfield(bitPos1, length1);
return((u, d) =>
{
var imm = Constant.Create(d.arch.WordWidth, mask.Read(u));
d.state.ops.Add(new ImmediateOperand(imm));
return true;
});
}
// F - 5-bit floating point register encoding.
private static Mutator <MicroMipsDisassembler> F(int bitpos)
{
var field = new Bitfield(bitpos, 5);
return((u, d) =>
{
var iReg = (int)field.Read(u);
d.ops.Add(new RegisterOperand(d.arch.fpuRegs[iReg]));
return true;
});
}
private static Mutator <Avr32Disassembler> Imm_unsignedShifted(PrimitiveType dt, int bitPos, int length, int shift)
{
var bitfield = new Bitfield(bitPos, length);
return((u, d) =>
{
var imm = bitfield.Read(u) << shift;
d.ops.Add(new ImmediateOperand(Constant.Create(dt, imm)));
return true;
});
}
private static Mutator <Avr32Disassembler> Register(int bitpos)
{
var bitfield = new Bitfield(bitpos, 4);
return((u, d) =>
{
var iReg = bitfield.Read(u);
var reg = Registers.GpRegisters[iReg];
d.ops.Add(new RegisterOperand(reg));
return true;
});
}
// Compressed format floating point register (fr')
private static Mutator <RiscVDisassembler> Fc(int bitPos)
{
var regMask = new Bitfield(bitPos, 3);
return((u, d) =>
{
var iReg = compressedRegs[regMask.Read(u)];
var reg = new RegisterOperand(d.arch.FpRegs[iReg]);
d.state.ops.Add(reg);
return true;
});
}
// Integer register
private static Mutator <RiscVDisassembler> R(int bitPos)
{
var regMask = new Bitfield(bitPos, 5);
return((u, d) =>
{
var iReg = (int)regMask.Read(u);
var reg = new RegisterOperand(d.arch.GetRegister(iReg));
d.state.ops.Add(reg);
return true;
});
}
// m - memory access: base + offset with 3-bit register encoding
private static bool mb(uint uInstr, MicroMipsDisassembler dasm)
{
var encodedBase = baseField16.Read(uInstr);
var iBase = threeBitRegisterEncodings[encodedBase];
var baseReg = dasm.arch.GetRegister(iBase);
var encOffset = offsetField16.Read(uInstr);
var offset = encodedByteOffsets[encOffset];
var mop = new IndirectOperand(PrimitiveType.Byte, offset, baseReg);
dasm.ops.Add(mop);
return(true);
}
private static Mutator <Avr32Disassembler> DoubleRegister(int bitPos)
{
var bitfield = new Bitfield(bitPos, 3);
return((u, d) =>
{
var iReg = bitfield.Read(u) << 1;
var gp = Registers.GpRegisters;
d.ops.Add(new RegisterPairOperand(gp[iReg + 1], gp[iReg]));
return true;
});
}
// UIs - unsigned immediate, then shifted left.
private static Mutator <MicroMipsDisassembler> UIs(int bitPos, int length, int shift)
{
var field = new Bitfield(bitPos, length);
return((u, d) =>
{
var i = field.Read(u) << shift;
var imm = new ImmediateOperand(Constant.Create(d.arch.WordWidth, i));
d.ops.Add(imm);
return true;
});
}
// r - 3-bit register encoding.
private static Mutator <MicroMipsDisassembler> r(int bitpos, int [] encoding)
{
var field = new Bitfield(bitpos, 3);
return((u, d) =>
{
var iReg = field.Read(u);
var iReg32 = encoding[iReg];
d.ops.Add(new RegisterOperand(d.arch.GetRegister(iReg32)));
return true;
});
}
private static Mutator <Avr32Disassembler> Mrelative(RegisterStorage baseReg, int bitpos, int length)
{
var bitfield = new Bitfield(bitpos, length);
return((u, d) =>
{
var iOffset = (int)bitfield.Read(u) << 2;
var mem = MemoryOperand.Displaced(PrimitiveType.Word32, baseReg, iOffset);
d.ops.Add(mem);
return true;
});
}
private static Mutator <Avr32Disassembler> Mpre(PrimitiveType dt, int bitpos)
{
var bitfield = new Bitfield(bitpos, 4);
return((u, d) =>
{
var iReg = bitfield.Read(u);
var reg = Registers.GpRegisters[iReg];
d.ops.Add(MemoryOperand.PreDec(dt, reg));
return true;
});
}
private static Mutator <Avr32Disassembler> M(PrimitiveType dt, int baseRegPos)
{
var baseRegField = new Bitfield(baseRegPos, 4);
return((u, d) =>
{
var iReg = baseRegField.Read(u);
var reg = Registers.GpRegisters[iReg];
d.ops.Add(MemoryOperand.Displaced(dt, reg, 0));
return true;
});
}