private static bool RSYb(ulong uInstr, zSeriesDisassembler dasm)
{
var r1 = Registers.GpRegisters[(uInstr >> 36) & 0xF];
var m3 = (byte)((uInstr >> 32) & 0xF);
var b2 = Registers.GpRegisters[(uInstr >> 28) & 0xF];
var d2 = Bitfield.ReadSignedFields(rsya_offset, (uint)uInstr);
dasm.ops.Add(new RegisterOperand(r1));
dasm.ops.Add(ImmediateOperand.Byte(m3));
dasm.ops.Add(dasm.CreateAccess(b2, d2));
return true;
}
private static Mutator <MilStd1750Disassembler> Reg(int bitpos)
{
var bitfield = new Bitfield(bitpos, 4);
return((u, d) =>
{
var iReg = bitfield.Read(u);
d.ops.Add(new RegisterOperand(Registers.GpRegs[iReg]));
return true;
});
}
private static bool RXYa(ulong uInstr, zSeriesDisassembler dasm)
{
var r1 = new RegisterOperand(Registers.GpRegisters[(uInstr >> 36) & 0xF]);
var x2 = Registers.GpRegisters[(uInstr >> 32) & 0xF];
var b2 = Registers.GpRegisters[(uInstr >> 28) & 0xF];
var d2 = Bitfield.ReadSignedFields(rxya_offset, (uint)uInstr);
dasm.state.ops.Add(r1);
dasm.state.ops.Add(dasm.CreateAccess(b2, x2, d2));
return(true);
}
internal static Mutator <PowerPcDisassembler> s(int bitOffset, int len)
{
var field = new Bitfield(bitOffset, len);
return((u, d) =>
{
var op = new ImmediateOperand(Constant.Int32(field.ReadSigned(u)));
d.ops.Add(op);
return true;
});
}
private static Mutator <MCoreDisassembler> Imm(int bitpos, int bitlen)
{
var immField = new Bitfield(bitpos, bitlen);
return((u, d) =>
{
var imm = immField.Read(u);
d.ops.Add(ImmediateOperand.Word32(imm));
return true;
});
}
private static Mutator <Avr32Disassembler> Imm_signedShifted(int bitPos, int length, int shift)
{
var bitfield = new Bitfield(bitPos, length);
return((u, d) =>
{
var imm = bitfield.ReadSigned(u) << shift;
d.ops.Add(ImmediateOperand.Word32(imm));
return true;
});
}
/// <summary>
/// Register.
/// </summary>
private static Mutator <C166Disassembler> R(int bitPos, RegisterStorage [] regs)
{
var regField = new Bitfield(bitPos, 4);
return((u, d) =>
{
var reg = regs[regField.Read(u)];
d.ops.Add(new RegisterOperand(reg));
return true;
});
}
private static Mutator <OpenRISCDisassembler> Iu(int bitPos, int bitLength)
{
var field = new Bitfield(bitPos, bitLength);
return((u, d) =>
{
var n = field.Read(u);
d.ops.Add(new ImmediateOperand(Constant.Create(d.arch.WordWidth, n)));
return true;
});
}
public void CastToUShort_SameAsParsedFrom_True(ushort value)
{
// Arrange
Bitfield.Validate(value, out var bitfield);
// Act
var result = (ushort)bitfield;
// Assert
Assert.That(result, Is.EqualTo(value));
}
public void Version_Is_Correct(ushort value, int expectedVersion)
{
// Arrange
Bitfield.Validate(value, out var bitfield);
// Act
var version = bitfield.Version;
// Assert
Assert.That(version, Is.EqualTo(expectedVersion));
}
public void OperatorDoesNotEqual_UShort_True(ushort value)
{
// Arrange
Bitfield.Validate(value, out var bitfield);
// Act
var result = bitfield != (ushort)~value;
// Assert
Assert.That(result, Is.True);
}
public void Equals_MethodUShort_True(ushort value)
{
// Arrange
Bitfield.Validate(value, out var bitfield);
// Act
var result = bitfield.Equals(value);
// Assert
Assert.That(result, Is.True);
}
// rf: encoded register identifier in multiple fields.
private static Mutator<NanoMipsDisassembler> rf(Bitfield[] fields, int[] gprEncoding)
{
return (u, d) =>
{
var iEncodedReg = (int) Bitfield.ReadFields(fields, u);
var iReg = gprEncoding[iEncodedReg];
var reg = d.arch.GetRegister(iReg);
d.ops.Add(new RegisterOperand(reg));
return true;
};
}
// Rw: 5-bit register identifier from a wide instruction
private static WideMutator<NanoMipsDisassembler> Rw(int pos)
{
var field = new Bitfield(pos, 5);
return (u, d) =>
{
var iReg = (int) field.Read(u);
var reg = d.arch.GetRegister(iReg);
d.ops.Add(new RegisterOperand(reg));
return true;
};
}
private static Mutator <Cr16cDisassembler> Reg(int bitpos)
{
var regfield = new Bitfield(bitpos, 4);
return((u, d) =>
{
var ireg = regfield.Read(u);
d.ops.Add(new RegisterOperand(Registers.GpRegisters[ireg]));
return true;
});
}
private static Mutator <LatticeMico32Disassembler> PcRel(int bitpos, int bitsize)
{
var field = new Bitfield(bitpos, bitsize);
return((u, d) =>
{
var offset = field.ReadSigned(u) << 2;
d.ops.Add(AddressOperand.Create(d.addr + offset));
return true;
});
}
private static Mutator <V850Disassembler> Is(int bitpos, int bitlen)
{
var field = new Bitfield(bitpos, bitlen);
return((u, d) =>
{
var imm = field.ReadSigned(u);
d.ops.Add(ImmediateOperand.Word32(imm));
return true;
});
}
public static Mutator <Disassembler> Reg(int n)
{
var regField = new Bitfield(n, 4);
return((u, d) =>
{
var nReg = regField.Read(u);
d.operands.Add(RegOps[nReg]);
return true;
});
}
internal static Mutator <YmpDisassembler> ImmFrom(uint from, PrimitiveType dt, int bitpos, int bitlen)
{
var bitfield = new Bitfield(bitpos, bitlen);
return((u, d) =>
{
var imm = from - bitfield.Read(u);
d.ops.Add(new ImmediateOperand(Constant.Create(dt, imm)));
return true;
});
}
// F - 5-bit floating point register encoding.
private static Mutator <MicroMipsDisassembler> F(int bitpos)
{
var field = new Bitfield(bitpos, 5);
return((u, d) =>
{
var iReg = (int)field.Read(u);
d.ops.Add(new RegisterOperand(d.arch.fpuRegs[iReg]));
return true;
});
}
private static Mutator <YmpDisassembler> Imm(PrimitiveType dt, int bitpos, int bitlen, uint nFrom)
{
var bitfield = new Bitfield(bitpos, bitlen);
return((u, d) =>
{
var imm = bitfield.Read(u);
d.ops.Add(new ImmediateOperand(Constant.Create(dt, nFrom - imm)));
return true;
});
}
private static Mutator <Avr32Disassembler> Imm_unsignedShifted(PrimitiveType dt, int bitPos, int length, int shift)
{
var bitfield = new Bitfield(bitPos, length);
return((u, d) =>
{
var imm = bitfield.Read(u) << shift;
d.ops.Add(new ImmediateOperand(Constant.Create(dt, imm)));
return true;
});
}
// Unsigned immediate
private static Mutator <RiscVDisassembler> Imm(int bitPos1, int length1)
{
var mask = new Bitfield(bitPos1, length1);
return((u, d) =>
{
var imm = Constant.Create(d.arch.WordWidth, mask.Read(u));
d.state.ops.Add(new ImmediateOperand(imm));
return true;
});
}
internal static Mutator <PowerPcDisassembler> u(int pos, int len)
{
var field = new Bitfield(pos, len);
return((u, d) =>
{
var op = new ImmediateOperand(Constant.Byte((byte)field.Read(u)));
d.ops.Add(op);
return true;
});
}
private static Mutator <LatticeMico32Disassembler> ImmS(int bitpos, int bitsize)
{
var field = new Bitfield(bitpos, bitsize);
return((u, d) =>
{
var imm = field.ReadSigned(u);
d.ops.Add(ImmediateOperand.Word32(imm));
return true;
});
}
public Bitfield ToBitfield()
{
Bitfield bitfield = new Bitfield(Size);
for (int i = 0; i < Size; i++)
{
bitfield[i] = this[i];
}
return(bitfield);
}
// Compressed format floating point register (fr')
private static Mutator <RiscVDisassembler> Fc(int bitPos)
{
var regMask = new Bitfield(bitPos, 3);
return((u, d) =>
{
var iReg = compressedRegs[regMask.Read(u)];
var reg = new RegisterOperand(d.arch.FpRegs[iReg]);
d.state.ops.Add(reg);
return true;
});
}
// UIs - unsigned immediate, then shifted left.
private static Mutator <MicroMipsDisassembler> UIs(int bitPos, int length, int shift)
{
var field = new Bitfield(bitPos, length);
return((u, d) =>
{
var i = field.Read(u) << shift;
var imm = new ImmediateOperand(Constant.Create(d.arch.WordWidth, i));
d.ops.Add(imm);
return true;
});
}
// Integer register
private static Mutator <RiscVDisassembler> R(int bitPos)
{
var regMask = new Bitfield(bitPos, 5);
return((u, d) =>
{
var iReg = (int)regMask.Read(u);
var reg = new RegisterOperand(d.arch.GetRegister(iReg));
d.state.ops.Add(reg);
return true;
});
}
// r - 3-bit register encoding.
private static Mutator <MicroMipsDisassembler> r(int bitpos, int [] encoding)
{
var field = new Bitfield(bitpos, 3);
return((u, d) =>
{
var iReg = field.Read(u);
var iReg32 = encoding[iReg];
d.ops.Add(new RegisterOperand(d.arch.GetRegister(iReg32)));
return true;
});
}