/*
* CD4001BC: Quad 2-Input NOR Buffered B Series Gate
*
* +--------------+
* A1 |1 ++ 14| VDD
* B1 |2 13| A6
* A2 |3 12| Y6
* Y2 |4 4001 11| A5
* A3 |5 10| Y5
* Y3 |6 9| A4
* VSS |7 8| Y4
* +--------------+
*
*/
//static NETLIST_START(CD4001_DIP)
public static void netlist_CD4001_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4001_GATE(setup, "A");
CD4001_GATE(setup, "B");
CD4001_GATE(setup, "C");
CD4001_GATE(setup, "D");
#endif
h.NET_C("A.VDD", "B.VDD", "C.VDD", "D.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS", "D.VSS");
h.DIPPINS( /* +--------------+ */
"A.A", /* A1 |1 ++ 14| VDD */ "A.VDD",
"A.B", /* B1 |2 13| B4 */ "D.B",
"A.Q", /* Y1 |3 12| A4 */ "D.A",
"B.Q", /* Y2 |4 4001 11| Y4 */ "D.Q",
"B.A", /* A2 |5 10| Y3 */ "C.Q",
"B.B", /* B2 |6 9| B3 */ "C.B",
"A.VSS", /* VSS |7 8| A3 */ "C.A"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4066_DIP
//- Title: CD4066BM/CD4066BC Quad Bilateral Switch
//- Pinalias: INOUTA,OUTINA,OUTINB,INOUTB,CONTROLB,CONTROLC,VSS,INOUTC,OUTINC,OUTIND,INOUTD,CONTROLD,CONTROLA,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005665.PDF
//-
//static NETLIST_START(CD4066_DIP)
public static void netlist_CD4066_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4066_GATE(setup, "A");
CD4066_GATE(setup, "B");
CD4066_GATE(setup, "C");
CD4066_GATE(setup, "D");
#endif
h.NET_C("A.VDD", "B.VDD", "C.VDD", "D.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS", "D.VSS");
h.PARAM("A.BASER", 270.0);
h.PARAM("B.BASER", 270.0);
h.PARAM("C.BASER", 270.0);
h.PARAM("D.BASER", 270.0);
h.DIPPINS( /* +--------------+ */
"A.R.1", /* INOUTA |1 ++ 14| VDD */ "A.VDD",
"A.R.2", /* OUTINA |2 13| CONTROLA */ "A.CTL",
"B.R.1", /* OUTINB |3 12| CONTROLD */ "D.CTL",
"B.R.2", /* INOUTB |4 4066 11| INOUTD */ "D.R.1",
"B.CTL", /* CONTROLB |5 10| OUTIND */ "D.R.2",
"C.CTL", /* CONTROLC |6 9| OUTINC */ "C.R.1",
"A.VSS", /* VSS |7 8| INOUTC */ "C.R.2"
/* +--------------+ */
);
h.NETLIST_END();
}
/* 2102: 1024 x 1-bit Static RAM
*
* +--------------+
* A6 |1 ++ 16| A7
* A5 |2 15| A8
* RWQ |3 14| A9
* A1 |4 82S16 13| CEQ
* A2 |5 12| DO
* A3 |6 11| DI
* A4 |7 10| VCC
* A0 |8 9| GND
* +--------------+
*/
//static NETLIST_START(RAM_2102A_DIP)
public static void netlist_RAM_2102A_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
RAM_2102A(A);
#endif
h.DIPPINS( /* +--------------+ */
"A.A6", /* A6 |1 ++ 16| A7 */ "A.A7",
"A.A5", /* A5 |2 15| A8 */ "A.A8",
"A.RWQ", /* RWQ |3 14| A9 */ "A.A9",
"A.A1", /* A1 |4 82S16 13| CEQ */ "A.CEQ",
"A.A2", /* A2 |5 12| DO */ "A.DO",
"A.A3", /* A3 |6 11| DI */ "A.DI",
"A.A4", /* A4 |7 10| VCC */ "A.VCC",
"A.A0", /* A0 |8 9| GND */ "A.GND"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4013_DIP
//- Title: CD4013BM/CD4013BC Dual D Flip-Flop
//- Pinalias: Q1,QQ1,CLOCK1,RESET1,DATA1,SET1,VSS,SET2,DATA2,RESET2,CLOCK2,QQ2,Q2,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/150/108670_DS.pdf
//-
//- +-----+---+---+---++---+----+
//- | CLK | D | R | S || Q | QQ |
//- +=====+===+===+===++===+====+
//- | 0-1 | 0 | 0 | 0 || 0 | 1 |
//- | 0-1 | 1 | 0 | 0 || 1 | 0 |
//- | 1-0 | X | 0 | 0 || Q | QQ |
//- | X | X | 1 | 0 || 0 | 1 |
//- | X | X | 0 | 1 || 1 | 0 |
//- | X | X | 1 | 1 || 1 | 1 |
//- +-----+---+---+---++---+----+
//-
//static NETLIST_START(CD4013_DIP)
public static void netlist_CD4013_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4013(setup, "A");
CD4013(setup, "B");
#endif
h.NET_C("A.VDD", "B.VDD");
h.NET_C("A.VSS", "B.VSS");
h.DIPPINS( /* +--------------+ */
"A.Q", /* Q1 |1 ++ 14| VDD */ "A.VDD",
"A.QQ", /* Q1Q |2 13| Q2 */ "B.Q",
"A.CLOCK", /* CLOCK1 |3 12| Q2Q */ "B.QQ",
"A.RESET", /* RESET1 |4 4013 11| CLOCK2 */ "B.CLOCK",
"A.DATA", /* DATA1 |5 10| RESET2 */ "B.RESET",
"A.SET", /* SET1 |6 9| DATA2 */ "B.DATA",
"A.VSS", /* VSS |7 8| SET2 */ "B.SET"
/* +--------------+ */
);
h.NETLIST_END();
}
/* DM82S16: 256 Bit bipolar ram
*
* +--------------+
* A1 |1 ++ 16| VCC
* A0 |2 15| A2
* CE1Q |3 14| A3
* CE2Q |4 82S16 13| DIN
* CE3Q |5 12| WEQ
* DOUTQ |6 11| A7
* A4 |7 10| A6
* GND |8 9| A5
* +--------------+
*
* Naming conventions follow Signetics datasheet
*/
//static NETLIST_START(TTL_82S16_DIP)
public static void netlist_TTL_82S16_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
TTL_82S16(A);
#endif
h.DIPPINS( /* +--------------+ */
"A.A1", /* A1 |1 ++ 16| VCC */ "A.VCC",
"A.A0", /* A0 |2 15| A2 */ "A.A2",
"A.CE1Q", /* CE1Q |3 14| A3 */ "A.A3",
"A.CE2Q", /* CE2Q |4 82S16 13| DIN */ "A.DIN",
"A.CE3Q", /* CE3Q |5 12| WEQ */ "A.WEQ",
"A.DOUTQ", /* DOUTQ |6 11| A7 */ "A.A7",
"A.A4", /* A4 |7 10| A6 */ "A.A6",
"A.GND", /* GND |8 9| A5 */ "A.A5"
/* +--------------+ */
);
h.NETLIST_END();
}
/* 82S115: 4K-bit TTL bipolar PROM (512 x 8)
*
* +--------------+
* A3 |1 ++ 24| VCC
* A4 |2 23| A2
* A5 |3 22| A1
* A6 |4 82S115 21| A0
* A7 |5 20| CE1Q
* A8 |6 19| CE2
* O1 |7 18| STROBE
* O2 |8 17| O8
* O3 |9 16| O7
* O4 |10 15| O6
* FE2 |11 14| O5
* GND |12 13| FE1
* +--------------+
*/
//static NETLIST_START(PROM_82S115_DIP)
public static void netlist_PROM_82S115_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
PROM_82S115(A);
NC_PIN(setup, "NC");
#endif
h.DIPPINS( /* +--------------+ */
"A.A3", /* A3 |1 ++ 24| VCC */ "A.VCC",
"A.A4", /* A4 |2 23| A2 */ "A.A2",
"A.A5", /* A5 |3 22| A1 */ "A.A1",
"A.A6", /* A6 |4 82S115 21| A0 */ "A.A0",
"A.A7", /* A7 |5 20| CE1Q */ "A.CE1Q",
"A.A8", /* A8 |6 19| CE2 */ "A.CE2",
"A.O1", /* O1 |7 18| STROBE */ "A.STROBE",
"A.O2", /* O2 |8 17| O8 */ "A.O8",
"A.O3", /* O3 |9 16| O7 */ "A.O7",
"A.O4", /* O4 |10 15| O6 */ "A.O6",
"NC.I", /* FE2 |11 14| O5 */ "A.O5",
"A.GND", /* GND |12 13| FE1 */ "NC.I"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4069_DIP
//- Title: CD4069UBM/CD4069UBC Inverter Circuits
//- Pinalias: A1,Y1,A2,Y2,A3,Y3,VSS,Y4,A4,Y5,A5,Y6,A6,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/150/206783_DS.pdf
//-
//static NETLIST_START(CD4069_DIP)
public static void netlist_CD4069_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4069_GATE(setup, "A");
CD4069_GATE(setup, "B");
CD4069_GATE(setup, "C");
CD4069_GATE(setup, "D");
CD4069_GATE(setup, "E");
CD4069_GATE(setup, "F");
#endif
h.NET_C("A.VDD", "B.VDD", "C.VDD", "D.VDD", "E.VDD", "F.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS", "D.VSS", "E.VSS", "F.VSS");
h.DIPPINS( /* +--------------+ */
"A.A", /* A1 |1 ++ 14| VDD */ "A.VDD",
"A.Q", /* Y1 |2 13| A6 */ "F.A",
"B.A", /* A2 |3 12| Y6 */ "F.Q",
"B.Q", /* Y2 |4 4069 11| A5 */ "E.A",
"C.A", /* A3 |5 10| Y5 */ "E.Q",
"C.Q", /* Y3 |6 9| A4 */ "D.A",
"A.VSS", /* VSS |7 8| Y4 */ "D.Q"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4070_DIP
//- Title: CD4070BM/CD4070BC Quad 2-Input EXCLUSIVE-OR Gate
//- Pinalias: A,B,J,K,C,D,VSS,E,F,L,M,G,H,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/150/206783_DS.pdf
//-
//static NETLIST_START(CD4070_DIP)
public static void netlist_CD4070_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4070_GATE(setup, "A");
CD4070_GATE(setup, "B");
CD4070_GATE(setup, "C");
CD4070_GATE(setup, "D");
#endif
h.NET_C("A.VDD", "B.VDD", "C.VDD", "D.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS", "D.VSS");
h.DIPPINS( /* +--------------+ */
"A.A", /* A |1 ++ 14| VDD */ "A.VDD",
"A.B", /* B |2 13| H */ "D.B",
"A.Q", /* J |3 12| G */ "D.A",
"B.Q", /* K |4 4070 11| M */ "D.Q",
"B.A", /* C |5 10| L */ "C.Q",
"B.B", /* D |6 9| F */ "C.B",
"A.VSS", /* VSS |7 8| E */ "C.A"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4006_DIP
//- Title: CD4006BM/CD4006BC 18-Stage Static Shift Register
//- Pinalias: D1,NC,CLOCK,D2,D3,D4,VSS,D4P4,D4P5,D3P4,D2P4,D2P5,D1P4,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005942.PDF
//-
//static NETLIST_START(CD4006_DIP)
public static void netlist_CD4006_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4006(setup, "A");
NC_PIN(setup, "NC");
#endif
h.DIPPINS( /* +--------------+ */
"A.D1", /* D1 |1 ++ 14| VDD */ "A.VDD",
"NC.I", /* NC |2 13| D1+4 */ "A.D1P4",
"A.CLOCK", /* CLOCK |3 12| D2+5 */ "A.D2P5",
"A.D2", /* D2 |4 4006 11| D2+4 */ "A.D2P4",
"A.D3", /* D3 |5 10| D3+4 */ "A.D3P4",
"A.D4", /* D4 |6 9| D4+5 */ "A.D4P5",
"A.VSS", /* VSS |7 8| D4+4 */ "A.D4P4"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4022_DIP
//- Title: CD4022BM/CD4022BC Divide-by-8 Counter/Divider with 8 Decoded Outputs
//- Pinalias: Q1,Q0,Q2,Q5,Q6,NC,Q3,VSS,NC,Q7,Q4,CARRY_OUT,CLOCK_ENABLE,CLOCK,RESET,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/166/108736_DS.pdf
//-
//static NETLIST_START(CD4022_DIP)
public static void netlist_CD4022_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4022(A);
NC_PIN(setup, "NC");
#endif
h.DIPPINS( /* +--------------+ */
"A.Q1", /* Q1 |1 ++ 16| VDD */ "A.VDD",
"A.Q0", /* Q0 |2 15| RESET */ "A.RESET",
"A.Q2", /* Q2 |3 14| CLOCK */ "A.CLK",
"A.Q5", /* Q5 |4 4022 13| CLOCK ENABLE */ "A.CLKEN",
"A.Q6", /* Q6 |5 12| CARRY OUT */ "A.CO",
"NC.I", /* NC |6 11| Q4 */ "A.Q4",
"A.Q3", /* Q3 |7 10| Q7 */ "A.Q7",
"A.VSS", /* VSS |8 9| NC */ "NC.I"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4538_DIP
//- Title: CD4538BC Dual Precision Monostable
//- Pinalias: C1,RC1,CLRQ1,B1,A1,Q1,QQ1,GND,QQ2,Q2,A2,B2,CLRQ2,RC2,C2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
//- Limitations:
//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
//-
//- Example: 74123.cpp,74123_example
//-
//- FunctionTable:
//- https://pdf1.alldatasheet.com/datasheet-pdf/view/50871/FAIRCHILD/CD4538.html
//-
//static NETLIST_START(CD4538_DIP)
public static void netlist_CD4538_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4538(setup, "A");
CD4538(setup, "B");
#endif
h.NET_C("A.VDD", "B.VDD");
h.NET_C("A.VSS", "B.VSS");
h.DIPPINS( /* +--------------+ */
"A.C", /* 1Z |1 ++ 16| VCC */ "A.VDD",
"A.RC", /* 1Y |2 15| 1S */ "B.C",
"A.CLRQ", /* 2Y |3 14| 4S */ "B.RC",
"A.A", /* 2Z |4 4316 13| 4Z */ "B.CLRQ",
"A.B", /* 2S |5 12| 4Y */ "B.A",
"A.Q", /* 3S |6 11| 3Y */ "B.B",
"A.QQ", /* EQ |7 10| 3Z */ "B.Q",
"A.VSS", /* GND |8 9| VEE */ "B.QQ"
/* +--------------+ */
);
h.NETLIST_END();
}
/*
* Generic layout with 1 opamp, VCC+ on pin 7, VCC- on pin 4 and compensation
* // FIXME: Offset inputs are not supported!
*/
//static NETLIST_START(opamp_layout_1_7_4)
public static void netlist_opamp_layout_1_7_4(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.DIPPINS( /* +--------------+ */
"NC" /* OFFSET */, /* |1 ++ 8| */ "NC",
"A.MINUS", /* |2 7| */ "A.VCC",
"A.PLUS", /* |3 6| */ "A.OUT",
"A.GND", /* |4 5| */ "NC" /* OFFSET */
/* +--------------+ */
);
h.NETLIST_END();
}
/*
* Generic layout with 2 opamps, VCC on pin 8 and GND on pin 4
*/
//static NETLIST_START(opamp_layout_2_8_4)
public static void netlist_opamp_layout_2_8_4(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.DIPPINS( /* +--------------+ */
"A.OUT", /* |1 ++ 8| */ "A.VCC",
"A.MINUS", /* |2 7| */ "B.OUT",
"A.PLUS", /* |3 6| */ "B.MINUS",
"A.GND", /* |4 5| */ "B.PLUS"
/* +--------------+ */
);
h.NET_C("A.GND", "B.GND");
h.NET_C("A.VCC", "B.VCC");
h.NETLIST_END();
}
/*
* Generic layout with 2 opamps, VCC+ on pins 9/13, VCC- on pin 4 and compensation
*/
//static NETLIST_START(opamp_layout_2_13_9_4)
public static void netlist_opamp_layout_2_13_9_4(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.DIPPINS( /* +--------------+ */
"A.MINUS", /* |1 ++ 14| */ "A.N2",
"A.PLUS", /* |2 13| */ "A.VCC",
"A.N1", /* |3 12| */ "A.OUT",
"A.GND", /* |4 11| */ "NC",
"B.N1", /* |5 10| */ "B.OUT",
"B.PLUS", /* |6 9| */ "B.VCC",
"B.MINUS", /* |7 8| */ "B.N2"
/* +--------------+ */
);
h.NET_C("A.GND", "B.GND");
h.NETLIST_END();
}
/*
* Generic layout with 1 opamp, VCC+ on pin 8, VCC- on pin 5 and compensation
*/
//static NETLIST_START(opamp_layout_1_8_5)
public static void netlist_opamp_layout_1_8_5(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.DIPPINS( /* +--------------+ */
"NC.1", /* |1 10| */ "NC.3",
"OFFSET.N1", /* |2 9| */ "NC.2",
"MINUS", /* |3 8| */ "VCC.PLUS",
"PLUS", /* |4 7| */ "OUT",
"VCC.MINUS", /* |5 6| */ "OFFSET.N2"
/* +--------------+ */
);
h.NET_C("A.GND", "VCC.MINUS");
h.NET_C("A.VCC", "VCC.PLUS");
h.NET_C("A.MINUS", "MINUS");
h.NET_C("A.PLUS", "PLUS");
h.NET_C("A.OUT", "OUT");
h.NETLIST_END();
}
//- Identifier: CD4316_DIP
//- Title: 74HC/HCT4316 Quad bilateral switches
//- Pinalias: 1Z,1Y,2Y,2Z,2S,3S,EQ,GND,VEE,3Z,3Y,4Y,4Z,4S,1S,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Philips datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheet/philips/74HCT4316.pdf
//-
//static NETLIST_START(CD4316_DIP)
public static void netlist_CD4316_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4316_GATE(setup, "A");
CD4316_GATE(setup, "B");
CD4316_GATE(setup, "C");
CD4316_GATE(setup, "D");
#endif
h.NET_C("A.E", "B.E", "C.E", "D.E");
h.NET_C("A.VDD", "B.VDD", "C.VDD", "D.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS", "D.VSS");
h.PARAM("A.BASER", 45.0);
h.PARAM("B.BASER", 45.0);
h.PARAM("C.BASER", 45.0);
h.PARAM("D.BASER", 45.0);
h.DIPPINS( /* +--------------+ */
"A.R.2", /* 1Z |1 ++ 16| VCC */ "A.VDD",
"A.R.1", /* 1Y |2 15| 1S */ "A.S",
"B.R.1", /* 2Y |3 14| 4S */ "D.S",
"B.R.2", /* 2Z |4 4316 13| 4Z */ "D.R.2",
"B.S", /* 2S |5 12| 4Y */ "D.R.1",
"C.S", /* 3S |6 11| 3Y */ "C.R.1",
"A.E", /* EQ |7 10| 3Z */ "C.R.2",
"A.VSS", /* GND |8 9| VEE */ "VEE"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4020_DIP
//- Title: CD4020BC 14-Stage Ripple Carry Binary Counters
//- Pinalias: Q12,Q13,Q14,Q6,Q5,Q7,Q4,VSS,Q1,PHI1,RESET,Q9,Q8,Q10,Q11,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/90/109006_DS.pdf
//-
//static NETLIST_START(CD4020_DIP)
public static void netlist_CD4020_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4020(setup, "A");
#endif
h.DIPPINS( /* +--------------+ */
"A.Q12", /* Q12 |1 ++ 16| VDD */ "A.VDD",
"A.Q13", /* Q13 |2 15| Q11 */ "A.Q11",
"A.Q14", /* Q14 |3 14| Q10 */ "A.Q10",
"A.Q6", /* Q6 |4 4020 13| Q8 */ "A.Q8",
"A.Q5", /* Q5 |5 12| Q9 */ "A.Q9",
"A.Q7", /* Q7 |6 11| RESET */ "A.RESET",
"A.Q4", /* Q4 |7 10| PHI1 */ "A.IP",
"A.VSS", /* VSS |8 9| Q1 */ "A.Q1"
/* +--------------+ */);
h.NETLIST_END();
}
/*
* Generic layout with 1 opamp, VCC+ on pin 11, VCC- on pin 6 and compensation
*/
//static NETLIST_START(opamp_layout_1_11_6)
public static void netlist_opamp_layout_1_11_6(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.DIPPINS( /* +--------------+ */
"NC.1", /* |1 ++ 14| */ "NC.7",
"NC.2", /* |2 13| */ "NC.6",
"OFFSET.N1", /* |3 12| */ "NC.5",
"MINUS", /* |4 11| */ "VCC.PLUS",
"PLUS", /* |5 10| */ "OUT",
"VCC.MINUS", /* |6 9| */ "OFFSET.N2",
"NC.3", /* |7 8| */ "NC.4"
/* +--------------+ */
);
h.NET_C("A.GND", "VCC.MINUS");
h.NET_C("A.VCC", "VCC.PLUS");
h.NET_C("A.MINUS", "MINUS");
h.NET_C("A.PLUS", "PLUS");
h.NET_C("A.OUT", "OUT");
h.NETLIST_END();
}
//- Identifier: CD4053_DIP
//- Title: CD4053BM/CD4053BC Triple 2-Channel AnalogMultiplexer/Demultiplexer
//- Pinalias: INOUTBY,INOUTBX,INOUTCY,OUTINC,INOUTCX,INH,VEE,VSS,C,B,A,INOUTAX,INOUTAY,OUTINA,OUTINB,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005662.PDF
//-
//static NETLIST_START(CD4053_DIP)
public static void netlist_CD4053_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4053_GATE(A);
CD4053_GATE(B);
CD4053_GATE(C);
#endif
h.NET_C("A.VEE", "B.VEE", "C.VEE");
h.NET_C("A.VDD", "B.VDD", "C.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS");
h.NET_C("A.INH", "B.INH", "C.INH");
h.PARAM("A.BASER", 270.0);
h.PARAM("B.BASER", 270.0);
h.PARAM("C.BASER", 270.0);
h.DIPPINS( /* +--------------+ */
"B.Y", /* INOUTBY |1 ++ 16| VDD */ "A.VDD",
"B.X", /* INOUTBX |2 15| OUTINB */ "B.XY",
"C.Y", /* INOUTCY |3 14| OUTINA */ "A.XY",
"C.XY", /* OUTINC |4 4053 13| INOUTAY */ "A.Y",
"C.X", /* INOUTCX |5 12| INOUTAX */ "A.X",
"A.INH", /* INH |6 11| A */ "A.S",
"A.VEE", /* VEE |7 10| B */ "B.S",
"A.VSS", /* VSS |8 9| C */ "C.S"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4024_DIP
//- Title: CD4024BM/CD4024BC 7-Stage Ripple Carry Binary Counter
//- Pinalias: IP,RESET,Q7,Q6,Q5,Q4,VSS,NC,Q3,NC,Q2,Q1,NC,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/120/108894_DS.pdf
//-
//static NETLIST_START(CD4024_DIP)
public static void netlist_CD4024_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4024(A);
NC_PIN(setup, "NC");
#endif
h.DIPPINS( /* +--------------+ */
"A.IP", /* IP |1 ++ 14| VDD */ "A.VDD",
"A.RESET", /* RESET |2 13| NC */ "NC.I",
"A.Q7", /* Q7 |3 12| Q1 */ "A.Q1",
"A.Q6", /* Q6 |4 4024 11| Q2 */ "A.Q2",
"A.Q5", /* Q5 |5 10| NC */ "NC.I",
"A.Q4", /* Q4 |6 9| Q3 */ "A.Q3",
"A.VSS", /* VSS |7 8| NC */ "NC.I"
/* +--------------+ */);
h.NETLIST_END();
}
