//- Identifier: CD4022_DIP
//- Title: CD4022BM/CD4022BC Divide-by-8 Counter/Divider with 8 Decoded Outputs
//- Pinalias: Q1,Q0,Q2,Q5,Q6,NC,Q3,VSS,NC,Q7,Q4,CARRY_OUT,CLOCK_ENABLE,CLOCK,RESET,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/166/108736_DS.pdf
//-
//static NETLIST_START(CD4022_DIP)
public static void netlist_CD4022_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4022(A);
NC_PIN(setup, "NC");
#endif
h.DIPPINS( /* +--------------+ */
"A.Q1", /* Q1 |1 ++ 16| VDD */ "A.VDD",
"A.Q0", /* Q0 |2 15| RESET */ "A.RESET",
"A.Q2", /* Q2 |3 14| CLOCK */ "A.CLK",
"A.Q5", /* Q5 |4 4022 13| CLOCK ENABLE */ "A.CLKEN",
"A.Q6", /* Q6 |5 12| CARRY OUT */ "A.CO",
"NC.I", /* NC |6 11| Q4 */ "A.Q4",
"A.Q3", /* Q3 |7 10| Q7 */ "A.Q7",
"A.VSS", /* VSS |8 9| NC */ "NC.I"
/* +--------------+ */
);
h.NETLIST_END();
}
//NETLIST_START(NE556_DIP)
public static void netlist_NE556_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
NE555(A)
NE555(B)
NET_C(A.GND, B.GND)
NET_C(A.VCC, B.VCC)
DIPPINS( /* +--------------+ */
A.DISCH, /* 1DISCH |1 ++ 14| VCC */ A.VCC,
A.THRESH, /* 1THRES |2 13| 2DISCH */ B.DISCH,
A.CONT, /* 1CONT |3 12| 2THRES */ B.THRESH,
A.RESET, /* 1RESET |4 NE556 11| 2CONT */ B.CONT,
A.OUT, /* 1OUT |5 10| 2RESET */ B.RESET,
A.TRIG, /* 1TRIG |6 9| 2OUT */ B.OUT,
A.GND, /* GND |7 8| 2TRIG */ B.TRIG
/* +--------------+ */
)
#endif
h.NETLIST_END();
}
/* 2102: 1024 x 1-bit Static RAM
*
* +--------------+
* A6 |1 ++ 16| A7
* A5 |2 15| A8
* RWQ |3 14| A9
* A1 |4 82S16 13| CEQ
* A2 |5 12| DO
* A3 |6 11| DI
* A4 |7 10| VCC
* A0 |8 9| GND
* +--------------+
*/
//static NETLIST_START(RAM_2102A_DIP)
public static void netlist_RAM_2102A_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
RAM_2102A(A);
#endif
h.DIPPINS( /* +--------------+ */
"A.A6", /* A6 |1 ++ 16| A7 */ "A.A7",
"A.A5", /* A5 |2 15| A8 */ "A.A8",
"A.RWQ", /* RWQ |3 14| A9 */ "A.A9",
"A.A1", /* A1 |4 82S16 13| CEQ */ "A.CEQ",
"A.A2", /* A2 |5 12| DO */ "A.DO",
"A.A3", /* A3 |6 11| DI */ "A.DI",
"A.A4", /* A4 |7 10| VCC */ "A.VCC",
"A.A0", /* A0 |8 9| GND */ "A.GND"
/* +--------------+ */
);
h.NETLIST_END();
}
//static NETLIST_START(ROM_MCM14524_DIP)
public static void netlist_ROM_MCM14524_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
ROM_MCM14524(A)
DEFPARAM(ROM, "unknown")
PARAM(A.ROM, "$(@.ROM)")
/* Motorola MCM14524: */
DIPPINS( /* +-----..-----+ */
A.CLK, /* /CLK |1 16| VDD */ A.VCC,
A.EN, /* CE |2 15| A0 */ A.A0,
A.B0, /* B0 |3 MCM 14| A1 */ A.A1,
A.B1, /* B1 |4 14524 13| A7 */ A.A7,
A.B2, /* B2 |5 12| A6 */ A.A6,
A.B3, /* B3 |6 11| A5 */ A.A5,
A.A2, /* A2 |7 10| A4 */ A.A4,
A.GND, /* VSS |8 9| A3 */ A.A3
/* +------------+ */
)
#endif
h.NETLIST_END();
}
//static NETLIST_START(ROM_TMS4800_DIP)
public static void netlist_ROM_TMS4800_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
ROM_TMS4800(A)
DIPPINS( /* +----------------+ */
A.VSS, /* VSS |1 ++ 24| OE1 */ A.OE1,
A.A1, /* A1 |2 23| O1 */ A.O1,
A.A2, /* A2 |3 22| O2 */ A.O2,
A.A3, /* A3 |4 TMS-4800 21| O3 */ A.O3,
A.A4, /* A4 |5 20| O4 */ A.O4,
A.A5, /* A5 |6 19| O5 */ A.O5,
A.A6, /* A6 |7 18| O6 */ A.O6,
A.A10, /* A10 |8 17| O7 */ A.O7,
A.VGG, /* VGG |9 16| O8 */ A.O8,
A.A9, /* A9 |10 15| A11 */ A.A11,
A.A8, /* A8 |11 14| OE2 */ A.OE2,
A.A7, /* A7 |12 13| AR */ A.AR
/* +----------------+ */
)
#endif
h.NETLIST_END();
}
/* 82S115: 4K-bit TTL bipolar PROM (512 x 8)
*
* +--------------+
* A3 |1 ++ 24| VCC
* A4 |2 23| A2
* A5 |3 22| A1
* A6 |4 82S115 21| A0
* A7 |5 20| CE1Q
* A8 |6 19| CE2
* O1 |7 18| STROBE
* O2 |8 17| O8
* O3 |9 16| O7
* O4 |10 15| O6
* FE2 |11 14| O5
* GND |12 13| FE1
* +--------------+
*/
//static NETLIST_START(PROM_82S115_DIP)
public static void netlist_PROM_82S115_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
PROM_82S115(A);
NC_PIN(setup, "NC");
#endif
h.DIPPINS( /* +--------------+ */
"A.A3", /* A3 |1 ++ 24| VCC */ "A.VCC",
"A.A4", /* A4 |2 23| A2 */ "A.A2",
"A.A5", /* A5 |3 22| A1 */ "A.A1",
"A.A6", /* A6 |4 82S115 21| A0 */ "A.A0",
"A.A7", /* A7 |5 20| CE1Q */ "A.CE1Q",
"A.A8", /* A8 |6 19| CE2 */ "A.CE2",
"A.O1", /* O1 |7 18| STROBE */ "A.STROBE",
"A.O2", /* O2 |8 17| O8 */ "A.O8",
"A.O3", /* O3 |9 16| O7 */ "A.O7",
"A.O4", /* O4 |10 15| O6 */ "A.O6",
"NC.I", /* FE2 |11 14| O5 */ "A.O5",
"A.GND", /* GND |12 13| FE1 */ "NC.I"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4013_DIP
//- Title: CD4013BM/CD4013BC Dual D Flip-Flop
//- Pinalias: Q1,QQ1,CLOCK1,RESET1,DATA1,SET1,VSS,SET2,DATA2,RESET2,CLOCK2,QQ2,Q2,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/150/108670_DS.pdf
//-
//- +-----+---+---+---++---+----+
//- | CLK | D | R | S || Q | QQ |
//- +=====+===+===+===++===+====+
//- | 0-1 | 0 | 0 | 0 || 0 | 1 |
//- | 0-1 | 1 | 0 | 0 || 1 | 0 |
//- | 1-0 | X | 0 | 0 || Q | QQ |
//- | X | X | 1 | 0 || 0 | 1 |
//- | X | X | 0 | 1 || 1 | 0 |
//- | X | X | 1 | 1 || 1 | 1 |
//- +-----+---+---+---++---+----+
//-
//static NETLIST_START(CD4013_DIP)
public static void netlist_CD4013_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4013(setup, "A");
CD4013(setup, "B");
#endif
h.NET_C("A.VDD", "B.VDD");
h.NET_C("A.VSS", "B.VSS");
h.DIPPINS( /* +--------------+ */
"A.Q", /* Q1 |1 ++ 14| VDD */ "A.VDD",
"A.QQ", /* Q1Q |2 13| Q2 */ "B.Q",
"A.CLOCK", /* CLOCK1 |3 12| Q2Q */ "B.QQ",
"A.RESET", /* RESET1 |4 4013 11| CLOCK2 */ "B.CLOCK",
"A.DATA", /* DATA1 |5 10| RESET2 */ "B.RESET",
"A.SET", /* SET1 |6 9| DATA2 */ "B.DATA",
"A.VSS", /* VSS |7 8| SET2 */ "B.SET"
/* +--------------+ */
);
h.NETLIST_END();
}
//static NETLIST_START(CD4081_DIP)
public static void netlist_CD4081_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4081_GATE(A)
CD4081_GATE(B)
CD4081_GATE(C)
CD4081_GATE(D)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
DIPPINS( /* +--------------+ */
A.A, /* A |1 ++ 14| VDD */ A.VDD,
A.B, /* B |2 13| H */ D.B,
A.Q, /* J |3 12| G */ D.A,
B.Q, /* K |4 4081 11| M */ D.Q,
B.A, /* C |5 10| L */ C.Q,
B.B, /* D |6 9| F */ C.B,
A.VSS, /* VSS |7 8| E */ C.A
/* +--------------+ */
)
#endif
h.NETLIST_END();
}
//static NETLIST_START(CD4030_DIP)
public static void netlist_CD4030_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4030_GATE(A)
CD4030_GATE(B)
CD4030_GATE(C)
CD4030_GATE(D)
DIPPINS( /* +--------------+ */
A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
A.B, /* B1 |2 13| B4 */ D.B,
A.Q, /* Y1 |3 12| A4 */ D.A,
B.Q, /* Y2 |4 4030 11| Y4 */ D.Q,
B.A, /* A2 |5 10| Y3 */ C.Q,
B.B, /* B2 |6 9| B3 */ C.B,
A.VSS, /* VSS |7 8| A3 */ C.A
/* +--------------+ */
)
#endif
h.NETLIST_END();
}
//- Identifier: CD4006_DIP
//- Title: CD4006BM/CD4006BC 18-Stage Static Shift Register
//- Pinalias: D1,NC,CLOCK,D2,D3,D4,VSS,D4P4,D4P5,D3P4,D2P4,D2P5,D1P4,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005942.PDF
//-
//static NETLIST_START(CD4006_DIP)
public static void netlist_CD4006_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4006(setup, "A");
NC_PIN(setup, "NC");
#endif
h.DIPPINS( /* +--------------+ */
"A.D1", /* D1 |1 ++ 14| VDD */ "A.VDD",
"NC.I", /* NC |2 13| D1+4 */ "A.D1P4",
"A.CLOCK", /* CLOCK |3 12| D2+5 */ "A.D2P5",
"A.D2", /* D2 |4 4006 11| D2+4 */ "A.D2P4",
"A.D3", /* D3 |5 10| D3+4 */ "A.D3P4",
"A.D4", /* D4 |6 9| D4+5 */ "A.D4P5",
"A.VSS", /* VSS |7 8| D4+4 */ "A.D4P4"
/* +--------------+ */
);
h.NETLIST_END();
}
//static NETLIST_START(CD4076_DIP)
public static void netlist_CD4076_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4076(A)
DIPPINS( /* +--------------+ */
A.OD1, /* OD1 |1 ++ 16| VDD */ A.VDD,
A.OD2, /* OD2 |2 15| CLR */ A.CLR,
A.OA, /* OA |3 14| IA */ A.IA,
A.OB, /* OB |4 4076 13| IB */ A.IB,
A.OC, /* OC |5 12| IC */ A.IC,
A.OD, /* OD |6 11| ID */ A.ID,
A.CLK, /* CLK |7 10| ID2 */ A.ID2,
A.VSS, /* VSS |8 9| ID1 */ A.ID1
/* +--------------+ */
)
#endif
h.NETLIST_END();
}
//- Identifier: CD4069_DIP
//- Title: CD4069UBM/CD4069UBC Inverter Circuits
//- Pinalias: A1,Y1,A2,Y2,A3,Y3,VSS,Y4,A4,Y5,A5,Y6,A6,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/150/206783_DS.pdf
//-
//static NETLIST_START(CD4069_DIP)
public static void netlist_CD4069_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4069_GATE(setup, "A");
CD4069_GATE(setup, "B");
CD4069_GATE(setup, "C");
CD4069_GATE(setup, "D");
CD4069_GATE(setup, "E");
CD4069_GATE(setup, "F");
#endif
h.NET_C("A.VDD", "B.VDD", "C.VDD", "D.VDD", "E.VDD", "F.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS", "D.VSS", "E.VSS", "F.VSS");
h.DIPPINS( /* +--------------+ */
"A.A", /* A1 |1 ++ 14| VDD */ "A.VDD",
"A.Q", /* Y1 |2 13| A6 */ "F.A",
"B.A", /* A2 |3 12| Y6 */ "F.Q",
"B.Q", /* Y2 |4 4069 11| A5 */ "E.A",
"C.A", /* A3 |5 10| Y5 */ "E.Q",
"C.Q", /* Y3 |6 9| A4 */ "D.A",
"A.VSS", /* VSS |7 8| Y4 */ "D.Q"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4070_DIP
//- Title: CD4070BM/CD4070BC Quad 2-Input EXCLUSIVE-OR Gate
//- Pinalias: A,B,J,K,C,D,VSS,E,F,L,M,G,H,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheets/150/206783_DS.pdf
//-
//static NETLIST_START(CD4070_DIP)
public static void netlist_CD4070_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4070_GATE(setup, "A");
CD4070_GATE(setup, "B");
CD4070_GATE(setup, "C");
CD4070_GATE(setup, "D");
#endif
h.NET_C("A.VDD", "B.VDD", "C.VDD", "D.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS", "D.VSS");
h.DIPPINS( /* +--------------+ */
"A.A", /* A |1 ++ 14| VDD */ "A.VDD",
"A.B", /* B |2 13| H */ "D.B",
"A.Q", /* J |3 12| G */ "D.A",
"B.Q", /* K |4 4070 11| M */ "D.Q",
"B.A", /* C |5 10| L */ "C.Q",
"B.B", /* D |6 9| F */ "C.B",
"A.VSS", /* VSS |7 8| E */ "C.A"
/* +--------------+ */
);
h.NETLIST_END();
}
//static NETLIST_START(CD4042_DIP)
public static void netlist_CD4042_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4042(A)
DIPPINS( /* +--------------+ */
A.Q4, /* Q4 |1 ++ 16| VDD */ A.VDD,
A.Q1, /* Q1 |2 15| Q4Q */ A.Q4Q,
A.Q1Q, /* Q1Q |3 14| D4 */ A.D4,
A.D1, /* D1 |4 4042 13| D3 */ A.D3,
A.CLK, /* CLK |5 12| Q3Q */ A.Q3Q,
A.POL, /* POL |6 11| Q3 */ A.Q3,
A.D2, /* D2 |7 10| Q2 */ A.Q2,
A.VSS, /* VSS |8 9| Q2Q */ A.Q2Q
/* +--------------+ */
)
#endif
h.NETLIST_END();
}
//- Identifier: CD4066_DIP
//- Title: CD4066BM/CD4066BC Quad Bilateral Switch
//- Pinalias: INOUTA,OUTINA,OUTINB,INOUTB,CONTROLB,CONTROLC,VSS,INOUTC,OUTINC,OUTIND,INOUTD,CONTROLD,CONTROLA,VDD
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//- FunctionTable:
//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005665.PDF
//-
//static NETLIST_START(CD4066_DIP)
public static void netlist_CD4066_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4066_GATE(setup, "A");
CD4066_GATE(setup, "B");
CD4066_GATE(setup, "C");
CD4066_GATE(setup, "D");
#endif
h.NET_C("A.VDD", "B.VDD", "C.VDD", "D.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS", "D.VSS");
h.PARAM("A.BASER", 270.0);
h.PARAM("B.BASER", 270.0);
h.PARAM("C.BASER", 270.0);
h.PARAM("D.BASER", 270.0);
h.DIPPINS( /* +--------------+ */
"A.R.1", /* INOUTA |1 ++ 14| VDD */ "A.VDD",
"A.R.2", /* OUTINA |2 13| CONTROLA */ "A.CTL",
"B.R.1", /* OUTINB |3 12| CONTROLD */ "D.CTL",
"B.R.2", /* INOUTB |4 4066 11| INOUTD */ "D.R.1",
"B.CTL", /* CONTROLB |5 10| OUTIND */ "D.R.2",
"C.CTL", /* CONTROLC |6 9| OUTINC */ "C.R.1",
"A.VSS", /* VSS |7 8| INOUTC */ "C.R.2"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: AN6551_SIL
//- Title: AN6551 Dual Operational Amplifier
//- Pinalias: VCC,A.OUT,A-,A+,GND,B+,B-,B.OUT,VCC
//- Package: SIL
//- NamingConvention: Naming conventions follow Panasonic datasheet
//- FunctionTable:
//- https://datasheetspdf.com/pdf-file/182163/PanasonicSemiconductor/AN6551/1
//-
//static NETLIST_START(AN6551_SIL)
public static void netlist_AN6551_SIL(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
OPAMP(setup, "A", "AN6551");
OPAMP(setup, "B", "AN6551");
#endif
h.NET_C("A.GND", "B.GND");
h.ALIAS("1", "A.VCC");
h.ALIAS("2", "A.OUT");
h.ALIAS("3", "A.MINUS");
h.ALIAS("4", "A.PLUS");
h.ALIAS("5", "A.GND");
h.ALIAS("6", "B.PLUS");
h.ALIAS("7", "B.MINUS");
h.ALIAS("8", "B.OUT");
h.ALIAS("9", "B.VCC");
h.NETLIST_END();
}
/* DM82S16: 256 Bit bipolar ram
*
* +--------------+
* A1 |1 ++ 16| VCC
* A0 |2 15| A2
* CE1Q |3 14| A3
* CE2Q |4 82S16 13| DIN
* CE3Q |5 12| WEQ
* DOUTQ |6 11| A7
* A4 |7 10| A6
* GND |8 9| A5
* +--------------+
*
* Naming conventions follow Signetics datasheet
*/
//static NETLIST_START(TTL_82S16_DIP)
public static void netlist_TTL_82S16_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
TTL_82S16(A);
#endif
h.DIPPINS( /* +--------------+ */
"A.A1", /* A1 |1 ++ 16| VCC */ "A.VCC",
"A.A0", /* A0 |2 15| A2 */ "A.A2",
"A.CE1Q", /* CE1Q |3 14| A3 */ "A.A3",
"A.CE2Q", /* CE2Q |4 82S16 13| DIN */ "A.DIN",
"A.CE3Q", /* CE3Q |5 12| WEQ */ "A.WEQ",
"A.DOUTQ", /* DOUTQ |6 11| A7 */ "A.A7",
"A.A4", /* A4 |7 10| A6 */ "A.A6",
"A.GND", /* GND |8 9| A5 */ "A.A5"
/* +--------------+ */
);
h.NETLIST_END();
}
//- Identifier: CD4538_DIP
//- Title: CD4538BC Dual Precision Monostable
//- Pinalias: C1,RC1,CLRQ1,B1,A1,Q1,QQ1,GND,QQ2,Q2,A2,B2,CLRQ2,RC2,C2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
//- Limitations:
//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
//-
//- Example: 74123.cpp,74123_example
//-
//- FunctionTable:
//- https://pdf1.alldatasheet.com/datasheet-pdf/view/50871/FAIRCHILD/CD4538.html
//-
//static NETLIST_START(CD4538_DIP)
public static void netlist_CD4538_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4538(setup, "A");
CD4538(setup, "B");
#endif
h.NET_C("A.VDD", "B.VDD");
h.NET_C("A.VSS", "B.VSS");
h.DIPPINS( /* +--------------+ */
"A.C", /* 1Z |1 ++ 16| VCC */ "A.VDD",
"A.RC", /* 1Y |2 15| 1S */ "B.C",
"A.CLRQ", /* 2Y |3 14| 4S */ "B.RC",
"A.A", /* 2Z |4 4316 13| 4Z */ "B.CLRQ",
"A.B", /* 2S |5 12| 4Y */ "B.A",
"A.Q", /* 3S |6 11| 3Y */ "B.B",
"A.QQ", /* EQ |7 10| 3Z */ "B.Q",
"A.VSS", /* GND |8 9| VEE */ "B.QQ"
/* +--------------+ */
);
h.NETLIST_END();
}
/*
* CD4001BC: Quad 2-Input NOR Buffered B Series Gate
*
* +--------------+
* A1 |1 ++ 14| VDD
* B1 |2 13| A6
* A2 |3 12| Y6
* Y2 |4 4001 11| A5
* A3 |5 10| Y5
* Y3 |6 9| A4
* VSS |7 8| Y4
* +--------------+
*
*/
//static NETLIST_START(CD4001_DIP)
public static void netlist_CD4001_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
CD4001_GATE(setup, "A");
CD4001_GATE(setup, "B");
CD4001_GATE(setup, "C");
CD4001_GATE(setup, "D");
#endif
h.NET_C("A.VDD", "B.VDD", "C.VDD", "D.VDD");
h.NET_C("A.VSS", "B.VSS", "C.VSS", "D.VSS");
h.DIPPINS( /* +--------------+ */
"A.A", /* A1 |1 ++ 14| VDD */ "A.VDD",
"A.B", /* B1 |2 13| B4 */ "D.B",
"A.Q", /* Y1 |3 12| A4 */ "D.A",
"B.Q", /* Y2 |4 4001 11| Y4 */ "D.Q",
"B.A", /* A2 |5 10| Y3 */ "C.Q",
"B.B", /* B2 |6 9| B3 */ "C.B",
"A.VSS", /* VSS |7 8| A3 */ "C.A"
/* +--------------+ */
);
h.NETLIST_END();
}
//static NETLIST_START(amp)
void netlist_amp(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.UA741_DIP8("X3A");
h.RES("R1", RES_K(2.2));
h.RES("R2", RES_K(4.7));
h.RES("VR", 200); // Actually a potentiometer
h.CAP("C1", CAP_U(0.15));
h.RES("RI", RES_K(100));
h.NET_C("X3A.2", "R1.1");
h.NET_C("X3A.6", "R1.2", "R2.1");
h.NET_C("R2.2", "VR.1");
h.NET_C("VR.1", "C1.1"); // 100% pot position
h.NET_C("C1.2", "RI.1");
h.NET_C("GND", "VR.2", "RI.2");
// Amplifier M51516L, assume input RI 100k
h.ALIAS("OPAMP", "X3A.2");
h.ALIAS("OUT", "RI.1");
h.ALIAS("VP", "X3A.7");
h.ALIAS("VM", "X3A.4");
h.ALIAS("GND", "X3A.3");
h.NETLIST_END();
}
//NETLIST_START(konami1x)
void netlist_konami1x(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.SOLVER("Solver", 48000);
h.ANALOG_INPUT("VP5", 5);
h.ANALOG_INPUT("VM5", -5);
h.LOCAL_SOURCE("filter", netlist_filter);
h.LOCAL_SOURCE("amp", netlist_amp);
h.LOCAL_SOURCE("AY1", netlist_AY1);
h.LOCAL_SOURCE("AY2", netlist_AY2);
h.INCLUDE("AY1");
h.NET_C("FCHA1.O", "FCHB1.O", "FCHC1.O");
h.SUBMODEL("amp", "AMP");
h.NET_C("VP5", "AMP.VP");
h.NET_C("GND", "AMP.GND");
h.NET_C("VM5", "AMP.VM");
h.NET_C("FCHA1.O", "AMP.OPAMP");
h.ALIAS("OUT", "AMP.OUT");
h.NETLIST_END();
}
//static NETLIST_START(filter)
void netlist_filter(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.CD4066_GATE("G1");
h.PARAM("G1.BASER", 270.0);
h.CD4066_GATE("G2");
h.PARAM("G2.BASER", 270.0);
h.RES("RI", RES_K(1));
h.RES("RO", RES_K(5));
h.CAP("C1", CAP_U(0.22));
h.CAP("C2", CAP_U(0.047));
h.NET_C("RI.2", "RO.1", "G1.R.1", "G2.R.1");
h.NET_C("G1.R.2", "C1.1");
h.NET_C("G2.R.2", "C2.1");
h.NET_C("C1.2", "C2.2", "G1.VSS", "G2.VSS");
h.NET_C("G1.VDD", "G2.VDD");
h.ALIAS("I", "RI.1");
h.ALIAS("O", "RO.2");
h.ALIAS("CTL1", "G1.CTL");
h.ALIAS("CTL2", "G2.CTL");
h.ALIAS("VDD", "G1.VDD");
h.ALIAS("VSS", "G1.VSS");
h.NETLIST_END();
}
//static NETLIST_START(MM5837_DIP)
public static void netlist_MM5837_DIP(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
throw new emu_unimplemented();
#if false
MM5837(A)
NC_PIN(NC)
// Create a parameter freq for the dip model
// The default will be A's FREQ parameter.
DEFPARAM(FREQ, "$(@.A.FREQ")
PARAM(A.FREQ, "$(@.FREQ)")
DIPPINS( /* +--------+ */
A.VDD, /* VDD |1 ++ 8| NC */ NC.I,
A.VGG, /* VGG |2 7| NC */ NC.I,
A.OUT, /* OUT |3 6| NC */ NC.I,
A.VSS, /* VSS |4 5| NC */ NC.I
/* +--------+ */
)
#endif
h.NETLIST_END();
}
//NETLIST_START(gunfight)
public static void netlist_gunfight(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.SOLVER("Solver", 48000);
h.PARAM("Solver.SORT_TYPE", "ASCENDING");
// For this netlist, ASCENDING turns out to be slightly faster than
// the default sort type of PREFER_IDENTITY_TOP_LEFT, but the
// difference when using static solvers is very small.
h.LOCAL_SOURCE("gunfight_schematics", netlist_gunfight_schematics);
h.INCLUDE("gunfight_schematics");
// The amplifying transistors all get 16-volt power. The raw AC power
// input from the main power supply to the game logic board is 16.5
// volts, but this is rectified and regulated to about 16 volts via
// TIP-31 power transistor Q301 and BZX61-C16 16-volt Zener diode
// D304.
h.ANALOG_INPUT("I_V16", 16); // 16-volt power for sound amplifiers
h.ANALOG_INPUT("I_V5", 5); // 5-volt power for logic input devices
h.LOGIC_INPUT("I_LEFT_SHOT", 0, "74XX");
h.LOGIC_INPUT("I_RIGHT_SHOT", 0, "74XX");
h.LOGIC_INPUT("I_LEFT_HIT", 0, "74XX");
h.LOGIC_INPUT("I_RIGHT_HIT", 0, "74XX");
// Power and ground connections for logic input devices:
h.NET_C("I_V5.Q",
"I_LEFT_SHOT.VCC", "I_RIGHT_SHOT.VCC",
"I_LEFT_HIT.VCC", "I_RIGHT_HIT.VCC");
h.NET_C("GND",
"I_LEFT_SHOT.GND", "I_RIGHT_SHOT.GND",
"I_LEFT_HIT.GND", "I_RIGHT_HIT.GND");
h.ALIAS("IN_LS", "I_LEFT_SHOT.Q");
h.ALIAS("IN_RS", "I_RIGHT_SHOT.Q");
h.ALIAS("IN_LH", "I_LEFT_HIT.Q");
h.ALIAS("IN_RH", "I_RIGHT_HIT.Q");
#if USE_FRONTIERS
// These frontiers keep the mostly independant halves of the circuit
// (left channel and right channel) from affecting each other and the
// noise generator, which speeds up processing substantially while
// making no audible change in the output. These seem to be the only
// frontiers which improve performance; I haven't been able to find
// any additional beneficial ones from examining the circuit and
// experimenting.
h.OPTIMIZE_FRONTIER("C303.1", RES_M(1), 50);
h.OPTIMIZE_FRONTIER("C306.1", RES_M(1), 50);
h.OPTIMIZE_FRONTIER("C304.1", RES_M(1), 50);
h.OPTIMIZE_FRONTIER("C305.1", RES_M(1), 50);
#endif
h.NETLIST_END();
}
//NETLIST_START(opamp_lib)
public static void netlist_opamp_lib(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.LOCAL_LIB_ENTRY("opamp_layout_4_4_11", netlist_opamp_layout_4_4_11);
h.LOCAL_LIB_ENTRY("opamp_layout_2_8_4", netlist_opamp_layout_2_8_4);
h.LOCAL_LIB_ENTRY("opamp_layout_2_13_9_4", netlist_opamp_layout_2_13_9_4);
h.LOCAL_LIB_ENTRY("opamp_layout_1_7_4", netlist_opamp_layout_1_7_4);
h.LOCAL_LIB_ENTRY("opamp_layout_1_8_5", netlist_opamp_layout_1_8_5);
h.LOCAL_LIB_ENTRY("opamp_layout_1_11_6", netlist_opamp_layout_1_11_6);
// FIXME: JFET Opamp may need better model
// VLL and VHH for +-6V RI=10^12 (for numerical stability 10^9 is used below
// RO from data sheet
h.NET_MODEL("TL084 OPAMP(TYPE=3 VLH=0.75 VLL=0.75 FPF=10 UGF=3000k SLEW=13M RI=1000M RO=192 DAB=0.0014)");
h.NET_MODEL("LM324 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.00075)");
h.NET_MODEL("LM358 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.001)");
h.NET_MODEL("MB3614 OPAMP(TYPE=3 VLH=1.4 VLL=0.02 FPF=3 UGF=1000k SLEW=0.6M RI=1000k RO=100 DAB=0.002)");
h.NET_MODEL("UA741 OPAMP(TYPE=3 VLH=1.0 VLL=1.0 FPF=5 UGF=1000k SLEW=0.5M RI=2000k RO=75 DAB=0.0017)");
h.NET_MODEL("LM747 OPAMP(TYPE=3 VLH=1.0 VLL=1.0 FPF=5 UGF=1000k SLEW=0.5M RI=2000k RO=50 DAB=0.0017)");
h.NET_MODEL("LM747A OPAMP(TYPE=3 VLH=2.0 VLL=2.0 FPF=5 UGF=1000k SLEW=0.7M RI=6000k RO=50 DAB=0.0015)");
h.NET_MODEL("LM748 OPAMP(TYPE=3 VLH=2.0 VLL=2.0 FPF=5 UGF=800k SLEW=0.7M RI=800k RO=60 DAB=0.001)");
// TI and Motorola Datasheets differ - below are Motorola values, SLEW is average of LH and HL
h.NET_MODEL("LM3900 OPAMP(TYPE=3 VLH=1.0 VLL=0.03 FPF=2k UGF=4M SLEW=10M RI=10M RO=2k DAB=0.0015)");
h.NET_MODEL("AN6551 OPAMP(TYPE=3 VLH=1.0 VLL=0.03 FPF=20 UGF=2M SLEW=1M RI=10M RO=200 DAB=0.0015)");
#if USE_LM3900_MODEL_1
NET_MODEL("LM3900_NPN1 NPN(IS=1E-14 BF=150 TF=1E-9 CJC=1E-12 CJE=1E-12 VAF=150 RB=100 RE=5 IKF=0.002)")
NET_MODEL("LM3900_PNP1 PNP(IS=1E-14 BF=40 TF=1E-7 CJC=1E-12 CJE=1E-12 VAF=150 RB=100 RE=5)")
#endif
h.LOCAL_LIB_ENTRY("MB3614_DIP", netlist_MB3614_DIP);
h.LOCAL_LIB_ENTRY("MC3340_DIP", netlist_MC3340_DIP);
h.LOCAL_LIB_ENTRY("TL081_DIP", netlist_TL081_DIP);
h.LOCAL_LIB_ENTRY("TL082_DIP", netlist_TL082_DIP);
h.LOCAL_LIB_ENTRY("TL084_DIP", netlist_TL084_DIP);
h.LOCAL_LIB_ENTRY("LM324_DIP", netlist_LM324_DIP);
h.LOCAL_LIB_ENTRY("LM348_DIP", netlist_LM348_DIP);
h.LOCAL_LIB_ENTRY("LM358_DIP", netlist_LM358_DIP);
h.LOCAL_LIB_ENTRY("LM2902_DIP", netlist_LM2902_DIP);
h.LOCAL_LIB_ENTRY("UA741_DIP8", netlist_UA741_DIP8);
h.LOCAL_LIB_ENTRY("UA741_DIP10", netlist_UA741_DIP10);
h.LOCAL_LIB_ENTRY("UA741_DIP14", netlist_UA741_DIP14);
h.LOCAL_LIB_ENTRY("MC1558_DIP", netlist_MC1558_DIP);
h.LOCAL_LIB_ENTRY("LM747_DIP", netlist_LM747_DIP);
h.LOCAL_LIB_ENTRY("LM747A_DIP", netlist_LM747A_DIP);
h.LOCAL_LIB_ENTRY("LM3900", netlist_LM3900);
h.LOCAL_LIB_ENTRY("AN6551_SIL", netlist_AN6551_SIL);
h.NETLIST_END();
}
//static TRUTHTABLE_START(CD4069_GATE, 1, 1, "")
static void netlist_CD4069_GATE(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.TRUTHTABLE_START(setup, "CD4069_GATE", 1, 1, "");
h.TT_HEAD("A|Q ");
h.TT_LINE("0|1|55");
h.TT_LINE("1|0|55");
h.TT_FAMILY("CD4XXX");
h.TRUTHTABLE_END();
}
//static NETLIST_START(UA741_DIP8)
public static void netlist_UA741_DIP8(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.OPAMP("A", "UA741");
h.INCLUDE("opamp_layout_1_7_4");
h.NETLIST_END();
}
//NETLIST_START(pong)
void netlist_pong(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.NETLIST_START(setup);
h.MEMREGION_SOURCE(this, "maincpu");
h.PARAM("NETLIST.USE_DEACTIVATE", 1);
h.INCLUDE("pong_schematics");
h.NETLIST_END();
}
//static TRUTHTABLE_START(CD4011_GATE, 2, 1, "")
static void netlist_CD4011_GATE(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.TRUTHTABLE_START(setup, "CD4011_GATE", 2, 1, "");
h.TT_HEAD("A,B|Q ");
h.TT_LINE("0,X|1|100");
h.TT_LINE("X,0|1|100");
h.TT_LINE("1,1|0|100");
h.TT_FAMILY("CD4XXX");
h.TRUTHTABLE_END();
}
//static TRUTHTABLE_START(MC14584B_GATE, 1, 1, "")
static void netlist_MC14584B_GATE(netlist.nlparse_t setup)
{
netlist.helper h = new netlist.helper();
h.TRUTHTABLE_START(setup, "MC14584B_GATE", 1, 1, "");
h.TT_HEAD(" A | Q ");
h.TT_LINE(" 0 | 1 |100");
h.TT_LINE(" 1 | 0 |100");
// 2.1V negative going and 2.7V positive going at 5V
h.TT_FAMILY("FAMILY(TYPE=CMOS IVL=0.42 IVH=0.54 OVL=0.05 OVH=0.05 ORL=10.0 ORH=10.0)");
h.TRUTHTABLE_END();
}
