/// <summary>
/// Immediate type.
/// </summary>
public static string I(VR4300.Instruction instruction, VR4300 cpu)
{
switch (instruction.RegImm)
{
case VR4300.RegImmOpCode.BGEZAL:
case VR4300.RegImmOpCode.BGEZL:
case VR4300.RegImmOpCode.BLTZ:
case VR4300.RegImmOpCode.BGEZ:
return(Format(instruction, FormatRegister(instruction.RS, cpu), (short)instruction.Immediate));
}
switch (instruction.OP)
{
case VR4300.OpCode.BEQ:
case VR4300.OpCode.BNE:
case VR4300.OpCode.BEQL:
case VR4300.OpCode.BNEL:
return(Format(instruction, FormatRegister(instruction.RS, cpu), FormatRegister(instruction.RT, cpu), (short)instruction.Immediate));
case VR4300.OpCode.BLEZL:
case VR4300.OpCode.BLEZ:
case VR4300.OpCode.BGTZ:
return(Format(instruction, FormatRegister(instruction.RS, cpu), (short)instruction.Immediate));
default:
return(Format(instruction, FormatRegister(instruction.RT, cpu), FormatRegister(instruction.RS, cpu), (short)instruction.Immediate));
}
}
/// <summary>
/// Register type.
/// </summary>
public static string R(VR4300.Instruction instruction, VR4300 cpu)
{
switch (instruction.Special)
{
case VR4300.SpecialOpCode.JALR:
return(Format(instruction, FormatRegister(instruction.RD, cpu), FormatRegister(instruction.RS, cpu)));
case VR4300.SpecialOpCode.JR:
case VR4300.SpecialOpCode.MTLO:
case VR4300.SpecialOpCode.MTHI:
return(Format(instruction, FormatRegister(instruction.RS, cpu)));
case VR4300.SpecialOpCode.MFHI:
case VR4300.SpecialOpCode.MFLO:
return(Format(instruction, FormatRegister(instruction.RD, cpu)));
case VR4300.SpecialOpCode.MULTU:
case VR4300.SpecialOpCode.DMULTU:
case VR4300.SpecialOpCode.DDIVU:
return(Format(instruction, FormatRegister(instruction.RS, cpu), FormatRegister(instruction.RT, cpu)));
case VR4300.SpecialOpCode.SLLV:
case VR4300.SpecialOpCode.SRLV:
return(Format(instruction, FormatRegister(instruction.RD, cpu), FormatRegister(instruction.RT, cpu), FormatRegister(instruction.RS, cpu)));
case VR4300.SpecialOpCode.SLL:
case VR4300.SpecialOpCode.SRL:
case VR4300.SpecialOpCode.DSLL32:
case VR4300.SpecialOpCode.DSRA32:
case VR4300.SpecialOpCode.SRA:
return(Format(instruction, FormatRegister(instruction.RD, cpu), FormatRegister(instruction.RT, cpu), (sbyte)instruction.SA));
}
return(Format(instruction, FormatRegister(instruction.RD, cpu), FormatRegister(instruction.RS, cpu), FormatRegister(instruction.RT, cpu)));
}
public static string CP0(VR4300.Instruction instruction, VR4300 cpu)
{
switch ((VR4300.SystemControlUnit.OpCode)instruction.RS)
{
case VR4300.SystemControlUnit.OpCode.MT:
case VR4300.SystemControlUnit.OpCode.MF:
return(Format(instruction, FormatRegister(instruction.RT, cpu), FormatCP0Register(instruction.RD, cpu)));
default:
return(FormatOpCode(instruction));
}
}
private static string FormatCP0Register(int index, VR4300 cpu) => RegisterPrefix + (VR4300.SystemControlUnit.RegisterIndex)index + (cpu != null ? FormatRegisterContents(cpu.CP0.Registers[index]) : string.Empty);
private static string FormatRegister(int index, VR4300 cpu) => RegisterPrefix + (VR4300.GPRIndex)index + (cpu != null ? FormatRegisterContents(cpu.GPR[index]) : string.Empty);
/// <summary>
/// Jump type.
/// </summary>
public static string J(VR4300.Instruction instruction, VR4300 cpu) => Format(instruction, $"0x{((cpu != null ? (cpu.DelaySlot ?? cpu.PC) : 0) & ~(ulong)((1 << 28) - 1)) | (instruction.Target << 2):X8}");
public SampleModule()
{
Get["/"] = _ => View["index.html"];
Post["/"] = r =>
{
var data = ((string)Request.Form["data"]).Replace("\n", string.Empty).Replace("\r", string.Empty).Replace(" ", string.Empty);
var instructionCount = Math.Min(data.Length / 8, 2048);
var instructions = new List <VR4300.Instruction>(instructionCount);
var ram = new byte[0x0100];
for (int i = 0; i < instructionCount; i++)
{
if (uint.TryParse(new string(data.Skip(i * 8).Take(8).ToArray()), NumberStyles.HexNumber, null, out var instruction))
{
instructions.Add(instruction);
}
else
{
return("BAD BAD BAD instruction");
}
}
var stop = false;
var maps = new[]
{
new MappingEntry(0x1FC00000, 0xC0000000)
{
Read = a =>
{
var index = (int)(a / 4);
if (index >= instructions.Count)
{
stop = true;
}
return(index < instructions.Count ? instructions[index] : 0);
}
},
new MappingEntry(0x00000000, (uint)ram.Length)
{
Read = a => BitConverter.ToUInt32(ram, (int)a),
Write = (a, v) => BitHelper.Write(ram, (int)a, v)
}
};
var cpu = new VR4300
{
ReadSysAD = maps.ReadWord,
WriteSysAD = maps.WriteWord
};
var timer = new Stopwatch();
cpu.Reset();
try
{
timer.Start();
while (!stop && timer.Elapsed < executionTimeLimit)
{
cpu.Cycle();
}
timer.Stop();
}
catch (Exception e)
{
return($"NOT OK !!! PLEASE UNDERSTAND {e.Message}");
}
var memory = new StringBuilder();
memory.AppendLine("Memory be like:");
memory.AppendLine();
for (int i = 0; i < ram.Length; i += sizeof(uint))
{
memory.AppendLine($"{i:X2}: 0x{BitConverter.ToUInt32(ram, i):X8}");
}
return(new TextResponse("OK !!!\n" + memory + $"\nRuntime like {timer.Elapsed}"));
};
}
