public Testbench_XilinxAdderSubtracter()
{
_m_clk = new Clock(ClockPeriod)
{
Clk = _clk
};
_m_signal = new XilinxAdderSubtracter()
{
CLK = _clk,
A = _A,
B = _B,
S = _S,
// CE = _CE,
//C_out = _C_out,
};
_m_logger4 = new ConsoleLogger<StdLogicVector>()
{
DataIn = _S
};
_m_logger1 = new ConsoleLogger<StdLogicVector>()
{
DataIn = _A
};
_m_logger2 = new ConsoleLogger<StdLogicVector>()
{
DataIn = _B
};
_m_logger3 = new ConsoleLogger<StdLogic>()
{
DataIn = _C_out
};
_m_logger5 = new ConsoleLogger<StdLogic>()
{
DataIn = _CE
};
}
public IXILMapping TryAllocate(Component host, XILInstr instr, TypeDescriptor[] operandTypes, TypeDescriptor[] resultTypes, IProject proj)
{
bool iisAdd = instr.Name == InstructionCodes.Add;
bool iisSub = instr.Name == InstructionCodes.Sub;
if (!iisAdd && !iisSub)
return null;
FixFormat fmta, fmtb, fmtr;
fmta = GetFixFormat(operandTypes[0]);
fmtb = GetFixFormat(operandTypes[1]);
fmtr = GetFixFormat(resultTypes[0]);
if (fmta == null || fmtb == null || fmtr == null)
return null;
bool expectSigned = fmta.IsSigned || fmtb.IsSigned;
if (expectSigned != fmtr.IsSigned)
return null;
if (fmta.FracWidth != fmtb.FracWidth ||
fmtr.FracWidth != fmta.FracWidth)
return null;
int expectedWidth = Math.Max(fmta.TotalWidth, fmtb.TotalWidth);
if (fmtr.TotalWidth != expectedWidth &&
fmtr.TotalWidth != (expectedWidth + 1))
return null;
var xproj = proj as XilinxProject;
if (xproj == null)
return null;
var asub = new XilinxAdderSubtracter()
{
AddMode = iisAdd ? XilinxAdderSubtracter.EAddMode.Add : XilinxAdderSubtracter.EAddMode.Subtract,
Atype = fmta.IsSigned ? XilinxAdderSubtracter.ESignedness.Signed : XilinxAdderSubtracter.ESignedness.Unsigned,
Awidth = fmta.TotalWidth,
Bconstant = false,
Btype = fmtb.IsSigned ? XilinxAdderSubtracter.ESignedness.Signed : XilinxAdderSubtracter.ESignedness.Unsigned,
Bwidth = fmtb.TotalWidth,
Implementation = XilinxAdderSubtracter.EImplementation.Fabric,
TargetDeviceFamily = xproj.DeviceFamily,
OutWidth = fmtr.TotalWidth,
LatencyConfiguration = XilinxAdderSubtracter.ELatencyConfiguration.Automatic
};
int scaledStages = (int)Math.Round(Config.PipeStageScaling * asub.Latency);
asub.LatencyConfiguration = XilinxAdderSubtracter.ELatencyConfiguration.Manual;
asub.Latency = scaledStages;
return new XILMapping(asub, iisAdd, false);
}
public XILMapping(XilinxAdderSubtracter host, bool isAdd, bool swap)
{
_host = host;
_isAdd = isAdd;
_swap = swap;
}
public TransactionSite(XilinxAdderSubtracter host) :
base(host)
{
_host = host;
}
public IXILMapping TryAllocate(Component host, XILInstr instr, TypeDescriptor[] operandTypes, TypeDescriptor[] resultTypes, IProject proj)
{
bool iisAdd = instr.Name == InstructionCodes.Add;
bool iisSub = instr.Name == InstructionCodes.Sub;
if (!iisAdd && !iisSub)
{
return(null);
}
FixFormat fmta, fmtb, fmtr;
fmta = GetFixFormat(operandTypes[0]);
fmtb = GetFixFormat(operandTypes[1]);
fmtr = GetFixFormat(resultTypes[0]);
if (fmta == null || fmtb == null || fmtr == null)
{
return(null);
}
bool expectSigned = fmta.IsSigned || fmtb.IsSigned;
if (expectSigned != fmtr.IsSigned)
{
return(null);
}
if (fmta.FracWidth != fmtb.FracWidth ||
fmtr.FracWidth != fmta.FracWidth)
{
return(null);
}
int expectedWidth = Math.Max(fmta.TotalWidth, fmtb.TotalWidth);
if (fmtr.TotalWidth != expectedWidth &&
fmtr.TotalWidth != (expectedWidth + 1))
{
return(null);
}
var xproj = proj as XilinxProject;
if (xproj == null)
{
return(null);
}
var asub = new XilinxAdderSubtracter()
{
AddMode = iisAdd ? XilinxAdderSubtracter.EAddMode.Add : XilinxAdderSubtracter.EAddMode.Subtract,
Atype = fmta.IsSigned ? XilinxAdderSubtracter.ESignedness.Signed : XilinxAdderSubtracter.ESignedness.Unsigned,
Awidth = fmta.TotalWidth,
Bconstant = false,
Btype = fmtb.IsSigned ? XilinxAdderSubtracter.ESignedness.Signed : XilinxAdderSubtracter.ESignedness.Unsigned,
Bwidth = fmtb.TotalWidth,
Implementation = XilinxAdderSubtracter.EImplementation.Fabric,
TargetDeviceFamily = xproj.DeviceFamily,
OutWidth = fmtr.TotalWidth,
LatencyConfiguration = XilinxAdderSubtracter.ELatencyConfiguration.Automatic
};
int scaledStages = (int)Math.Round(Config.PipeStageScaling * asub.Latency);
asub.LatencyConfiguration = XilinxAdderSubtracter.ELatencyConfiguration.Manual;
asub.Latency = scaledStages;
return(new XILMapping(asub, iisAdd, false));
}
public XILMapping(XilinxAdderSubtracter host, bool isAdd, bool swap)
{
_host = host;
_isAdd = isAdd;
_swap = swap;
}
public TransactionSite(XilinxAdderSubtracter host) :
base(host)
{
_host = host;
}