/// <summary> /// /// </summary> /// <returns></returns> public static string GetDataFromScale() { if (device != null) { device.Close(); } device = new UART(); device.Open( MyGlobal.MySetting.SerialPortName, MyGlobal.MySetting.SerialBaudRate, MyGlobal.MySetting.SerialDataBits, myConverter.FromStringToSerialParity(MyGlobal.MySetting.SerialParity), myConverter.FromStringToSerialStopBits(MyGlobal.MySetting.SerialStopBits) ); if (device == null) { return(null); } if (device.IsConnected() == false) { return(null); } //clear serial receive buffer string data = null; device.Read(); //wait time int wait_time; bool r = int.TryParse(MyGlobal.MySetting.WaitTime, out wait_time); wait_time = r ? wait_time : 100; Thread.Sleep(wait_time); //read newest data data = device.Read(); if (data == null) { return(null); } //process data string value = null; if (data.Contains("\r\n")) { string[] buffer = data.Split(new string[] { "\r\n" }, StringSplitOptions.None); value = buffer[buffer.Length - 2].Trim(); } device.Close(); return(value); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { float f1 = 0, f2 = 0; FPGA.Signal <float> result = 0; byte fpuOp = 0; FPGA.Signal <bool> fpuTrigger = false, fpuCompleted = false; FPGA.Config.Entity <IFPU>().Op(fpuTrigger, fpuCompleted, f1, f2, fpuOp, result); Sequential handler = () => { const int baud = 115200; UART.ReadFloat(baud, RXD, out f1); UART.ReadFloat(baud, RXD, out f2); UART.Read(baud, RXD, out fpuOp); fpuTrigger = true; FPGA.Runtime.WaitForAllConditions(fpuCompleted); UART.WriteFloat(baud, result, TXD); }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { byte data = 0; Sequential processingHandler = () => { DTOs.RoundTrip response = new DTOs.RoundTrip(); response.b = data; Drivers.JSON.SerializeToUART <DTOs.RoundTrip>(ref response, TXD); }; FPGA.Config.OnRegisterWritten(data, processingHandler); Sequential deserializeHandler = () => { UART.Read(115200, RXD, out data); }; const bool trigger = true; FPGA.Config.OnSignal(trigger, deserializeHandler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { bool internalTXD = true; FPGA.Config.Link(internalTXD, TXD); Sequential handler = () => { byte prev = 100, next = 0; while (true) { next = UART.Read(115200, RXD); UART.RegisteredWrite(115200, prev, out internalTXD); UART.RegisteredWrite(115200, next, out internalTXD); prev = next; } }; FPGA.Config.OnStartup(handler); }
public static void Bootstrap( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD, Action <byte, FPGA.SyncStream <byte> > testAction ) { const int baud = 115200; var stream = new FPGA.SyncStream <byte>(); Sequential <byte> streamHandler = (data) => { UART.Write(baud, data, TXD); }; FPGA.Config.OnStream <byte>(stream, streamHandler); Sequential handler = () => { byte data = 0; UART.Read(baud, RXD, out data); testAction(data, stream); }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { byte data = 0; UART.Read(115200, RXD, out data); Func <byte> dFunc = () => (byte)(data * 2); FPGA.Signal <bool> writeEnable = false; FPGA.Register <byte> result = new FPGA.Register <byte>(0); FPGA.Config.RegisterOverride(result, dFunc, writeEnable); FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, writeEnable)); UART.Write(115200, result, TXD); }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.OutputSignal <bool> LED1, FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { FPU.FPUScope(); const int width = 10; const int baud = 115200; while (true) { byte data = 0; UART.Read(baud, RXD, out data); uint length = GeneratorTools.ArrayLength(width); for (uint i = 0; i < length; i++) { uint reversed = FPGA.Runtime.Reverse(i, width); UART.WriteUnsigned32(baud, reversed, TXD); } } }; FPGA.Config.OnStartup(handler); Drivers.IsAlive.Blink(LED1); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential mainHandler = () => { byte data = 0; byte[] buff = new byte[1000]; for (int i = 0; i < 1000; i++) { UART.Read(115200, RXD, out data); buff[i] = data; } byte sum = 0; for (int i = 0; i < 1000; i++) { data = buff[i]; sum += data; } UART.Write(115200, sum, TXD); }; const bool trigger = true; FPGA.Config.OnSignal(trigger, mainHandler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { while (true) { byte start = UART.Read(115200, RXD); ulong result = 0; SequentialMath.Fibonacci(start, out result); for (byte i = 0; i < 8; i++) { byte data = (byte)result; UART.Write(115200, data, TXD); result = result >> 8; } } }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { bool internalTXD = true; FPGA.Config.Link(internalTXD, TXD); Sequential mainHandler = () => { byte data = 0; byte[] buff = new byte[] { 1, 2, 3, 4, 5 }; UART.Read(115200, RXD, out data); for (int i = 0; i < buff.Length; i++) { byte existing = 0; existing = buff[i]; UART.RegisteredWrite(115200, existing, out internalTXD); } }; FPGA.Config.OnStartup(mainHandler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { while (true) { byte data = UART.Read(115200, RXD); switch (data) { case 0: data = Increment(data); break; case 1: var result = Increment(data); data = result; break; } UART.Write(115200, data, TXD); } }; FPGA.Config.OnStartup(handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { const int baud = 115200; Sequential handler = () => { while (true) { byte op = 0; UART.Read(baud, RXD, out op); uint op1 = 0, op2 = 0; UART.ReadUnsigned32(baud, RXD, ref op1); UART.ReadUnsigned32(baud, RXD, ref op2); var result = TestMethod(op, (int)op1, (int)op2); UART.WriteUnsigned64(baud, (ulong)result, TXD); } }; FPGA.Config.OnStartup(handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { FPU.FPUScope(); const int baud = 115200; byte command = 0; float op1, op2, res = 0; while (true) { UART.ReadFloat(baud, RXD, out op1); UART.ReadFloat(baud, RXD, out op2); command = UART.Read(baud, RXD); FloatControllersOps.TestHandler(op1, op2, command, out res); UART.WriteFloat(baud, res, TXD); } }; FPGA.Config.OnStartup(handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD) { var stream = new FPGA.SyncStream <byte>(); Sequential <byte> streamHandler = (value) => { UART.Write(115200, value, TXD); }; FPGA.Config.OnStream(stream, streamHandler); Sequential handler = () => { byte data = 0; UART.Read(115200, RXD, out data); for (ushort i = 0; i < data; i++) { stream.Write((byte)i); } }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD) { var stream = new FPGA.SyncStream <byte>(); bool internalTXD = true; FPGA.Config.Link(internalTXD, TXD); object txdLock = new object(); Sequential <byte> streamHandler = (value) => { lock (txdLock) { UART.RegisteredWrite(115200, value, out internalTXD); } }; FPGA.Config.OnStream(stream, streamHandler, 2); Sequential handler = () => { byte data = 0; UART.Read(115200, RXD, out data); for (ushort i = 0; i < data; i++) { stream.Write((byte)i); } }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD) { bool internalTXD = true; FPGA.Config.Link(internalTXD, TXD); object txdLock = new object(); byte counter = 0; object counterLock = new object(); var transmitterStream = new FPGA.SyncStream <byte>(); Sequential <byte> transmitterStreamHandler = (value) => { lock (txdLock) { UART.RegisteredWrite(115200, value, out internalTXD); } }; FPGA.Config.OnStream(transmitterStream, transmitterStreamHandler, 2); var receiverStream = new FPGA.SyncStream <byte>(); Sequential <byte> receiverStreamHandler = (value) => { Func <uint> instanceId = () => FPGA.Config.InstanceId(); byte increment = 0; lock (counterLock) { increment = counter; counter++; } transmitterStream.Write((byte)(value + increment + instanceId())); }; FPGA.Config.OnStream(receiverStream, receiverStreamHandler, 3); Sequential handler = () => { byte data = 0; UART.Read(115200, RXD, out data); for (ushort i = 0; i < data; i++) { receiverStream.Write((byte)i); } }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
void Loop() { int counter = 0; while (true) { counter++; var data = new SensorData() { Temp = tempHumidSI70.TakeMeasurement().Temperature, Humid = tempHumidSI70.TakeMeasurement().RelativeHumidity, Light = lightSense.GetIlluminance() }; var jsonStr = Json.NETMF.JsonSerializer.SerializeObject(data); Debug.Print("kirim :" + jsonStr); PrintToLcd("send count: " + counter); sendData(jsonStr); Thread.Sleep(5000); byte[] rx_data = new byte[20]; if (UART.CanRead) { var count = UART.Read(rx_data, 0, rx_data.Length); if (count > 0) { Debug.Print("count:" + count); var hasil = new string(System.Text.Encoding.UTF8.GetChars(rx_data)); Debug.Print("read:" + hasil); txtStatus.Text = hasil; txtStatus.Invalidate(); //mac_rx 2 AABBCC } } var gas = gasSense.ReadProportion(); var light = lightSense.GetIlluminance(); var temp = tempHumidSI70.TakeMeasurement().Temperature; var humid = tempHumidSI70.TakeMeasurement().RelativeHumidity; displayT35.BacklightEnabled = true; var font = Resources.GetFont(Resources.FontResources.NinaB); txtTemp.Text = "Temp: " + System.Math.Round(temp) + "C"; txtGas.Text = "Gas: " + System.Math.Round(gas) + "%"; txtHumid.Text = "Humid: " + System.Math.Round(humid) + "%"; txtLight.Text = "Light: " + System.Math.Round(light) + "Lux"; txtTemp.Invalidate(); txtGas.Invalidate(); txtHumid.Invalidate(); txtLight.Invalidate(); window.Invalidate(); Thread.Sleep(2000); } }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD) { Sequential mainHandler = () => { const uint baud = 115200; byte data = UART.Read(115200, RXD); UART.Write(baud, data, TXD); }; FPGA.Config.OnStartup(mainHandler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD) { byte data = 0; FPGA.Signal <byte> externalInput = new FPGA.Signal <byte>(); FPGA.Config.Link(data, out externalInput); FPGA.Signal <byte> externalOutput = new FPGA.Signal <byte>(); FPGA.Signal <bool> externalTrigger = new FPGA.Signal <bool>(); FPGA.Signal <bool> externalReady = new FPGA.Signal <bool>(); Sequential handler = () => { data = UART.Read(115200, RXD); for (var i = 0; i < 3; i++) { byte result = 0; switch (i) { case 0: FPGA.Config.Entity <IConcreteExternalPackage1>().ExternalEntity(externalInput, externalOutput, externalTrigger, externalReady); externalTrigger = true; FPGA.Runtime.WaitForAllConditions(externalReady); result = externalOutput; break; case 1: NestedLevel1 <IConcreteExternalPackage1>(data, out result); break; case 2: NestedLevel2 <IConcreteExternalPackage2>(40, out result); break; } UART.Write(115200, result, TXD); } }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { const bool trigger = true; Sequential handler = () => { byte data = UART.Read(115200, RXD); UART.Write(115200, data, TXD); }; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { byte[] buff = new byte[4]; bool[] results = new bool[4]; const int baud = 115200; for (int i = 0; i < buff.Length; i++) { byte data = 0; UART.Read(baud, RXD, out data); buff[i] = data; } sbyte value1, value2, value3, value4; FPGA.Signal <bool> result1 = false, result2 = false, result3 = false, result4 = false; value1 = (sbyte)buff[0]; value2 = (sbyte)buff[1]; value3 = (sbyte)buff[2]; value4 = (sbyte)buff[3]; FPGA.Config.NeuralNet <sbyte>("nn1.json"); // simple interval wait for net to process data FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(1)); results[0] = result1; results[1] = result2; results[2] = result3; results[3] = result4; for (int i = 0; i < results.Length; i++) { bool data = false; data = results[i]; UART.Write(baud, (byte)(data ? 1 : 0), TXD); } }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static void ReadData( ref FPGA.Register <ulong> a00, ref FPGA.Register <ulong> a01, ref FPGA.Register <ulong> a02, ref FPGA.Register <ulong> a03, ref FPGA.Register <ulong> a04, ref FPGA.Register <ulong> a05, ref FPGA.Register <ulong> a06, ref FPGA.Register <ulong> a07, ref FPGA.Register <ulong> a08, ref FPGA.Register <ulong> a09, ref FPGA.Register <ulong> a10, ref FPGA.Register <ulong> a11, ref FPGA.Register <ulong> a12, ref FPGA.Register <ulong> a13, ref FPGA.Register <ulong> a14, ref FPGA.Register <ulong> a15, ref FPGA.Register <ulong> a16, ref FPGA.Register <ulong> a17, ref FPGA.Register <ulong> a18, ref FPGA.Register <ulong> a19, ref FPGA.Register <ulong> a20, ref FPGA.Register <ulong> a21, ref FPGA.Register <ulong> a22, ref FPGA.Register <ulong> a23, ref FPGA.Register <ulong> a24, FPGA.InputSignal <bool> RXD) { for (byte index = 0; index < 25; index++) { ulong data = 0; for (byte i = 0; i < 8; i++) { byte part = 0; UART.Read(115200, RXD, out part); data = ((ulong)part << 56) | (data >> 8); } FPGA.Runtime.Assign( FPGA.Expressions.AssignRegister(index == 0 ? data : (ulong)a00, a00), FPGA.Expressions.AssignRegister(index == 1 ? data : (ulong)a01, a01), FPGA.Expressions.AssignRegister(index == 2 ? data : (ulong)a02, a02), FPGA.Expressions.AssignRegister(index == 3 ? data : (ulong)a03, a03), FPGA.Expressions.AssignRegister(index == 4 ? data : (ulong)a04, a04), FPGA.Expressions.AssignRegister(index == 5 ? data : (ulong)a05, a05), FPGA.Expressions.AssignRegister(index == 6 ? data : (ulong)a06, a06), FPGA.Expressions.AssignRegister(index == 7 ? data : (ulong)a07, a07), FPGA.Expressions.AssignRegister(index == 8 ? data : (ulong)a08, a08), FPGA.Expressions.AssignRegister(index == 9 ? data : (ulong)a09, a09), FPGA.Expressions.AssignRegister(index == 10 ? data : (ulong)a10, a10), FPGA.Expressions.AssignRegister(index == 11 ? data : (ulong)a11, a11), FPGA.Expressions.AssignRegister(index == 12 ? data : (ulong)a12, a12), FPGA.Expressions.AssignRegister(index == 13 ? data : (ulong)a13, a13), FPGA.Expressions.AssignRegister(index == 14 ? data : (ulong)a14, a14), FPGA.Expressions.AssignRegister(index == 15 ? data : (ulong)a15, a15), FPGA.Expressions.AssignRegister(index == 16 ? data : (ulong)a16, a16), FPGA.Expressions.AssignRegister(index == 17 ? data : (ulong)a17, a17), FPGA.Expressions.AssignRegister(index == 18 ? data : (ulong)a18, a18), FPGA.Expressions.AssignRegister(index == 19 ? data : (ulong)a19, a19), FPGA.Expressions.AssignRegister(index == 20 ? data : (ulong)a20, a20), FPGA.Expressions.AssignRegister(index == 21 ? data : (ulong)a21, a21), FPGA.Expressions.AssignRegister(index == 22 ? data : (ulong)a22, a22), FPGA.Expressions.AssignRegister(index == 23 ? data : (ulong)a23, a23), FPGA.Expressions.AssignRegister(index == 24 ? data : (ulong)a24, a24)); } }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { const bool trigger = false; // this should never be triggered Sequential handler = () => { byte data = 0; UART.Read(115200, RXD, out data); UART.Write(115200, data, TXD); }; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { bool internalTXD = true; FPGA.Config.Link(internalTXD, TXD); Sequential mainHandler = () => { byte data = 0; byte[] buff = new byte[] { 0, 1, 2, 3, 4 }; for (int i = 0; i < buff.Length; i++) { UART.Read(115200, RXD, out data); UART.RegisteredWrite(115200, data, out internalTXD); byte existing = 0; existing = buff[i]; UART.RegisteredWrite(115200, existing, out internalTXD); buff[i] = (byte)(data + existing); } for (int i = 0; i < buff.Length; i++) { data = buff[i]; UART.RegisteredWrite(115200, data, out internalTXD); } byte sum = 0; for (int i = 0; i < buff.Length; i++) { data = buff[i]; sum += data; } UART.RegisteredWrite(115200, sum, out internalTXD); }; const bool trigger = true; FPGA.Config.OnSignal(trigger, mainHandler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { byte data = UART.Read(115200, RXD); byte result = 0; TestMethod(data, out result); UART.Write(115200, result, TXD); }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD) { FPGA.SyncStream <byte> tdxStream = new FPGA.SyncStream <byte>(); Sequential <byte> txdHandler = (value) => { UART.Write(115200, value, TXD); }; FPGA.Config.OnStream(tdxStream, txdHandler); byte data = 0; Sequential mainHandler = () => { data = UART.Read(115200, RXD); }; const bool trigger = true; FPGA.Config.OnSignal(trigger, mainHandler); Sequential handler1 = () => { if (data == 0) { return; } tdxStream.Write(1); }; Sequential handler2 = () => { if (data == 0) { return; } tdxStream.Write(2); }; FPGA.Config.OnTimer(TimeSpan.FromMilliseconds(100), handler1, handler2); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { const uint baud = 115200; while (true) { FPGA.Optimizations.AddOptimizer <DefaultOptimizer>(); byte data = UART.Read(115200, RXD); UART.Write(baud, data, TXD); } }; FPGA.Config.OnStartup(handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential mainHandler = () => { byte seed = UART.Read(115200, RXD); int sum = 0; Handler(seed, out sum); UART.Write(115200, (byte)sum, TXD); }; const bool trigger = true; FPGA.Config.OnSignal(trigger, mainHandler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { while (true) { byte start = 0; UART.Read(115200, RXD, out start); for (uint counter = 0; counter < 100; counter++) { ulong fib = 0; SequentialMath.Calculators.Fibonacci(counter, out fib); if (fib > uint.MaxValue) { break; } bool isPrime = false; SequentialMath.Calculators.IsPrime((uint)fib, out isPrime); if (isPrime) { for (byte i = 0; i < 4; i++) { byte data = (byte)fib; UART.Write(115200, data, TXD); fib = fib >> 8; } } } } }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { Sequential handler = () => { byte data = 0; ulong tmp = 0; ulong op1 = 0, op2 = 0; for (byte i = 0; i < 2; i++) { for (byte j = 0; j < 8; j++) { UART.Read(115200, RXD, out data); tmp = ((ulong)data << 56) | (tmp >> 8); } if (i == 0) { op1 = tmp; } else { op2 = tmp; } } tmp = op1 + op2; for (byte j = 0; j < 8; j++) { UART.Write(115200, (byte)tmp, TXD); tmp = tmp >> 8; } }; const bool trigger = true; FPGA.Config.OnSignal(trigger, handler); }