public void AddDeclaration(VerilogModule declaration)
{
if (this.moduleDeclarations.ContainsKey(declaration.Name))
{
if (this.moduleDeclarations[declaration.Name].Filename == declaration.Filename)
{
// In this case, there are multiple instantiations of the same module within
// the same file, probably due to an IFDEF statement
StringBuilder sb = new StringBuilder("Multiple module insantiations found:");
sb.AppendLine("\tModule: " + declaration.Name);
sb.AppendLine("\tFile: " + declaration.Filename);
sb.AppendLine("\tOriginal @ Line:" + moduleDeclarations[declaration.Name].InOutListEnd.Line);
sb.AppendLine("\tNew @ Line:" + declaration.InOutListEnd.Line);
sb.AppendLine("Use new module instantiation?");
DialogResult dr = MessageBox.Show(sb.ToString(), "VFile Parser: Module Instance Conflict", MessageBoxButtons.YesNo);
if (dr == DialogResult.Yes)
{
this.moduleDeclarations[declaration.Name] = declaration;
}
}
else
{
// In this case, we are updating an old declaration, typically due to
// replacing PossibleInstances with VerilogModuleInstances
this.moduleDeclarations[declaration.Name] = declaration;
}
}
else
{
this.moduleDeclarations.Add(declaration.Name, declaration);
}
}
/// <summary>
/// Updates DFFs to support error injections
/// </summary>
/// <param name="vMod"></param>
/// <param name="changeLog"></param>
private void UpdateDffs(InserterMode mode, VerilogModule vMod, FileChangeLog changeLog)
{
int i = 0;
foreach (DffInstance dff in vMod.LocalDffs)
{
if (dff.ParametersExist)
{
if (dff.ParametersNamed)
{
changeLog.ProposeChange(dff.ParameterBegin.Pos, " ." + ERROR_PARAMETER + "(" + ERROR_PARAMETER + "), ");
}
else
{
if (dff.ParamsInParens)
{
changeLog.ProposeChange(dff.ParameterBegin.Pos, " ." + ERROR_PARAMETER + "(" + ERROR_PARAMETER + "), .SIZE(");
changeLog.ProposeChange(dff.ParameterEnd.Pos, ") ");
}
else
{
changeLog.ProposeChange(dff.ParameterBegin.Pos, "( ." + ERROR_PARAMETER + "(" + ERROR_PARAMETER + "), .SIZE(");
changeLog.ProposeChange(dff.ParameterEnd.Pos, ")) ");
}
}
}
else
{
changeLog.ProposeChange(dff.ParameterBegin.Pos, " #( ." + ERROR_PARAMETER + "(" + ERROR_PARAMETER + ")) ");
}
changeLog.ProposeChange(dff.PortList.Pos, Environment.NewLine + ".err_en(lcl_err" + ((vMod.ErrorControlWidth > 1)? "[" + i + "]" : string.Empty) + "),");
i++;
}
}
public VerilogModule GetModule(string moduleName)
{
VerilogModule vMod = null;
this.moduleLibrary.TryGetValue(moduleName, out vMod);
return(vMod);
}
/// <summary>
/// Insert actual instantiation of shadow capture module
/// </summary>
/// <param name="vMod"></param>
/// <param name="changeLog"></param>
private void InstantiateShadowCapture(VerilogModule vMod, FileChangeLog changeLog)
{
StringBuilder shadowCapture = new StringBuilder(Environment.NewLine);
shadowCapture.AppendLine("\t//[Shadow Module Instantiation here]");
string discreteDffs, dffWidths, dclks;
DffWidthParameters(vMod, out discreteDffs, out dffWidths, out dclks);
shadowCapture.AppendLine("\tshadow_capture #(.DFF_BITS(" + vMod.NumLocalDffBits +
"), .USE_DCLK(" + ((vMod.LocalDffs.Count > 0) ? "1" : "0") +
"), .CHAINS_IN(" + vMod.NumChainsIn +
"), .CHAINS_OUT(" + vMod.NumChainsOut +
"), .DISCRETE_DFFS(" + discreteDffs +
"), .DFF_WIDTHS(" + dffWidths + ")) " +
SHADOW_MOD_NAME + "_" + vMod.Name + " (");
shadowCapture.AppendLine("\t\t.clk(" + SHADOW_CLOCK + "), ");
shadowCapture.AppendLine("\t\t.rst(" + SHADOW_RESET + "), ");
shadowCapture.AppendLine("\t\t.capture_en(" + CAPTURE_ENABLE + "), ");
shadowCapture.AppendLine("\t\t.dclk(" + dclks + "), ");
shadowCapture.AppendLine("\t\t.din(" + RouteLocalDffs(vMod) + "),");
shadowCapture.AppendLine("\t\t.dump_en(" + DUMP_ENABLE + "), ");
shadowCapture.AppendLine("\t\t.chains_in(" + RouteInstanceShadowChains(vMod) + "), ");
shadowCapture.AppendLine("\t\t.chains_in_vld(" + ((vMod.NumChainsIn > 0) ? INST_CHAINS_OUT_VALID : "") + "), ");
shadowCapture.AppendLine("\t\t.chains_in_done(" + ((vMod.NumChainsIn == 0) ? "" : INST_CHAINS_OUT_DONE) + "), ");
shadowCapture.AppendLine("\t\t.chain_dump_en(" + ((vMod.NumChainsIn == 0) ? "" : CHAINS_DUMP_ENABLE) + "), ");
shadowCapture.AppendLine("\t\t.chains_out(" + CHAINS_OUT + "), ");
shadowCapture.AppendLine("\t\t.chains_out_vld(" + CHAINS_OUT_VALID + "), ");
shadowCapture.AppendLine("\t\t.chains_out_done(" + CHAINS_OUT_DONE + ")");
shadowCapture.AppendLine("\t);");
changeLog.ProposeChange(vMod.PrevEndModule.Pos, shadowCapture.ToString());
string[] args = new string[] { vMod.Name, vMod.NumLocalDffBits.ToString(), vMod.NumChainsIn.ToString(), vMod.NumChainsOut.ToString(), discreteDffs.ToString() };
snapArgLog.AppendLine(string.Join(",", args));
}
private void ParseForModDeclarations(StringTokenizer tknzr, VerilogFile vFile)
{
SetupPrecompiler();
Token prevTok = null;
Token currTok = tknzr.Next();
while (true)
{
if (currTok.Kind == TokenKind.EOF)
{
break;
}
if (prevTok == null || prevTok.Kind == TokenKind.EOL)
{
RunPrecompiler(tknzr, ref prevTok, ref currTok);
if (currTok.Value == "module")
{
VerilogModule parsedModule = ParseModuleDeclaration(tknzr, vFile);
AssignDffErrorIds(parsedModule);
vFile.AddDeclaration(parsedModule);
}
}
prevTok = currTok;
currTok = tknzr.Next();
}
}
/// <summary>
/// Updates the modules instantiated within vMod by inserting shadow clock in and chain out ports.
/// </summary>
/// <param name="vMod"></param>
/// <param name="changeLog"></param>
private void UpdateInstantiations(InserterMode mode, VerilogModule vMod, FileChangeLog changeLog)
{
//Propose changes in order to generate finalized change list
int chainOutBit = 0;
foreach (VerilogModuleInstance vmi in vMod.InstantiatedModules)
{
StringBuilder update = new StringBuilder();//"," + Environment.NewLine);
if (mode == InserterMode.Error || mode == InserterMode.Both)
{
if (vmi.Type.ErrorControlWidth > 0)
{
String paramChange = String.Empty;
if (vmi.Parameterized)
{
if (vmi.ParametersNamed)
{
paramChange = " ." + ERROR_PARAMETER + "(" + ERROR_PARAMETER + "),";
}
else
{
paramChange = " " + ERROR_PARAMETER + ", ";
}
}
else
{
paramChange = " #(." + ERROR_PARAMETER + "(" + ERROR_PARAMETER + ")) ";
}
changeLog.ProposeChange(vmi.ParameterList.Pos, paramChange.ToString());
update.AppendLine("\t\t." + ERROR_ENABLE + "(" + vmi.InstanceName + "_" + ERROR_ENABLE + "), // [ERROR]");
update.AppendLine("\t\t." + ERROR_CONTROL + "(" + vmi.InstanceName + "_" + ERROR_CONTROL + ") // [ERROR]");
}
}
if (mode == InserterMode.Shadow || mode == InserterMode.Both)
{
if (vmi.Type.NumChainsOut > 0)
{
int chainOutBitUpperLimit = (chainOutBit + vmi.Type.NumChainsOut - 1);
string bitLimits = (chainOutBit == chainOutBitUpperLimit) ? ((vMod.NumChainsIn == 1) ? string.Empty : "[" + chainOutBit.ToString() + "]") : "[" + (chainOutBitUpperLimit + ":" + chainOutBit) + "]";
update.AppendLine(",");
update.AppendLine("\t\t." + SHADOW_CLOCK + "(" + SHADOW_CLOCK + "), // [SHADOW]");
update.AppendLine("\t\t." + SHADOW_RESET + "(" + SHADOW_RESET + "), // [SHADOW]");
update.AppendLine("\t\t." + CAPTURE_ENABLE + "(" + CAPTURE_ENABLE + "), // [SHADOW]");
update.AppendLine("\t\t." + DUMP_ENABLE + "(" + CHAINS_DUMP_ENABLE + bitLimits + "), // [SHADOW]");
update.AppendLine("\t\t." + CHAINS_OUT + "(" + INST_CHAINS_OUT + bitLimits + "), // [SHADOW]");
update.AppendLine("\t\t." + CHAINS_OUT_DONE + "(" + INST_CHAINS_OUT_DONE + bitLimits + "), // [SHADOW]");
update.AppendLine("\t\t." + CHAINS_OUT_VALID + "(" + INST_CHAINS_OUT_VALID + bitLimits + ") // [SHADOW]");
chainOutBit += vmi.Type.NumChainsOut;
}
}
if (update.ToString() == ("," + Environment.NewLine))
{
continue;
}
changeLog.ProposeChange(vmi.InOutListEnd.Pos, update.ToString());
}
}
private void InstantiateSubErrorSplitters(VerilogModule vMod, FileChangeLog changeLog)
{
if (vMod.InstantiatedModules.Count < 1)
{
return;
}
StringBuilder sesSB = new StringBuilder(Environment.NewLine);
sesSB.AppendLine("\t//[Sub Error Control Splitter Instantiations here]");
foreach (VerilogModuleInstance vmi in vMod.InstantiatedModules)
{
if (vmi.Type.ErrorControlWidth <= 0)
{
continue;
}
sesSB.AppendLine("\tsubErrCtrlSplitter #(" +
".INW(" + vMod.ErrorControlWidth + "), " +
".OUTW(" + vmi.Type.ErrorControlWidth + "), " +
".LOW(" + vmi.LowerLocalErrorId + "), " +
".HIGH(" + vmi.UpperLocalErrorId + ")) " +
ERROR_SUB_MOD_NAME + "_" + vmi.InstanceName + "(");
sesSB.AppendLine("\t\t.err_en(err_en),");
sesSB.AppendLine("\t\t.err_ctrl(err_ctrl),");
sesSB.AppendLine("\t\t.sub_err_en(" + vmi.InstanceName + "_" + ERROR_ENABLE + "),");
sesSB.AppendLine("\t\t.sub_err_ctrl(" + vmi.InstanceName + "_" + ERROR_CONTROL + ")");
sesSB.AppendLine("\t);");
sesSB.AppendLine(Environment.NewLine);
}
changeLog.ProposeChange(vMod.PrevEndModule.Pos, sesSB.ToString());
}
public SnapshotKeyGenerator(VerilogModule vMod)
{
this.vMod = vMod;
this.numChainsIn = vMod.NumChainsIn;
this.numChainsOut = vMod.NumChainsOut;
this.numDffBits = vMod.NumLocalDffBits;
this.localDffs = vMod.LocalDffs;
}
/*
* private SortedDictionary<string, string> inPorts;
* private SortedDictionary<string, string> outPorts;
* private SortedDictionary<string, string> inoutPorts;*/
public VerilogModuleInstance(VerilogModule parent, VerilogModule type, string instanceName, Token inoutListEnd)
{
this.parent = parent;
this.filename = parent.Filename;
this.moduleType = type;
this.instanceName = instanceName;
this.inoutListEnd = inoutListEnd;
}
private void DffWidthParameters(VerilogModule vMod, out string discreteDffs, out string dffWidths, out string dclks)
{
if (vMod.LocalDffs.Count == 0)
{
discreteDffs = string.Empty;
dffWidths = string.Empty;
dclks = string.Empty;
return;
}
List <int> commonClkWidths = new List <int>();
List <string> commonClks = new List <string>();
List <DffInstance> dffs = vMod.LocalDffs;
string currClk = dffs[0].ClockPort;
int currClkWidth = 0;
for (int i = 0; i < dffs.Count; i++)
{
if (currClk == dffs[i].ClockPort)
{
currClkWidth += dffs[i].Size;
}
else
{
commonClks.Add(currClk);
commonClkWidths.Add(currClkWidth);
currClk = dffs[i].ClockPort;
currClkWidth = dffs[i].Size;
}
if (i == dffs.Count - 1)
{
commonClks.Add(currClk);
commonClkWidths.Add(currClkWidth);
}
}
StringBuilder clkSB = new StringBuilder("{");
StringBuilder widthSB = new StringBuilder("{");
for (int i = 0; i < commonClks.Count; i++)
{
clkSB.Append(commonClks[i]);
widthSB.Append("32'd" + commonClkWidths[i]);
if (i != commonClks.Count - 1)
{
clkSB.Append(", ");
widthSB.Append(", ");
}
}
clkSB.Append("}");
widthSB.Append("}");
discreteDffs = commonClks.Count.ToString();
dffWidths = widthSB.ToString();
dclks = clkSB.ToString();
}
private void AssignDffErrorIds(VerilogModule vMod)
{
int i = 0;
foreach (DffInstance dff in vMod.LocalDffs)
{
dff.ErrorId = i;
i++;
}
}
public PossibleInstance(string typeName, string instanceName, VerilogModule parentModule, Token bookmark, Token inOutListEnd, bool paramsExist, bool paramsNamed, Token paramList)
{
this.typeName = typeName;
this.instanceName = instanceName;
this.filename = parentModule.Filename;
this.parent = parentModule;
this.bookmark = bookmark;
this.inOutListEnd = inOutListEnd;
this.paramsExist = paramsExist;
this.paramsNamed = paramsNamed;
this.paramList = paramList;
}
private void PopulateDisplayHeirarchy(TreeNode parent, VerilogModule module)
{
TreeNode moduleNode = new TreeNode(module.Name);
parent.Nodes.Add(moduleNode);
CheckPossibleInstantiations(module);
module.AssignLocalErrorIds();
foreach (VerilogModuleInstance vmi in module.InstantiatedModules)
{
PopulateDisplayHeirarchy(parent.Nodes[parent.Nodes.IndexOf(moduleNode)], vmi.Type);
}
}
public void AddModulesToLibrary(Dictionary <string, VerilogModule> modules)
{
foreach (KeyValuePair <string, VerilogModule> kvp in modules)
{
if (!this.moduleLibrary.ContainsKey(kvp.Key))
{
// Extract Module from dictionary and add to library
VerilogModule vMod = kvp.Value;
this.moduleLibrary.Add(vMod.Name, vMod);
// Add possible instances contained in the module to the library
foreach (KeyValuePair <string, List <PossibleInstance> > kvpLPI in vMod.PossibleInstances)
{
foreach (PossibleInstance pi in kvpLPI.Value)
{
if (!this.possibleInstancesLibrary.ContainsKey(pi.TypeName))
{
//If it's the first possible instance of its type, create a new list before adding the PossibleInstance to it
possibleInstancesLibrary.Add(pi.TypeName, new List <PossibleInstance>());
}
// Already other possible instances of the same type, add pi to list of instances
possibleInstancesLibrary[pi.TypeName].Add(pi);
}
// Check if any possibleInstances are defined by this module
if (this.possibleInstancesLibrary.ContainsKey(vMod.Name))
{
// If so, replace PossibleInstances with VerilogModuleInstances
List <PossibleInstance> piList = possibleInstancesLibrary[vMod.Name];
for (int i = 0; i < piList.Count; i++)
{
PossibleInstance pi = piList[i];
StringTokenizer tknzr = StringTokenizer.TokenizerFromFile(pi.Filename, pi.Bookmark);
VerilogModuleInstance vmi = parser.ParseModuleInstance(pi.ParentModule, tknzr, pi.Bookmark, vMod);
pi.ParentModule.AddModuleInstance(vmi);
//this.AddModulesToLibrary(this.parser.Reparse(piList[i]).DeclaredModules);
piList.RemoveAt(i);
if (piList.Count == 0)
{
possibleInstancesLibrary.Remove(vMod.Name);
}
}
}
}
}
else
{
// Reparsing: updating VerilogModule definitions to contain more module instantiations
this.moduleLibrary[kvp.Key] = kvp.Value;
}
}
}
private void CheckPossibleInstantiations(VerilogModule vMod)
{
Dictionary <string, List <PossibleInstance> > tempInsts = new Dictionary <string, List <PossibleInstance> >(vMod.PossibleInstances);
foreach (KeyValuePair <string, List <PossibleInstance> > piEntry in tempInsts)
{
string pInstName = piEntry.Key;
if (IsModule(pInstName))
{
vMod.ReplacePossibleInstances(GetModule(pInstName));
}
}
}
public void DisplayModuleHeirarchy(TreeView display, VerilogModule root)
{
display.Nodes.Clear();
VerilogModuleTreeNode rootNode = new VerilogModuleTreeNode(root);
display.Nodes.Add(rootNode);
CheckPossibleInstantiations(root);
root.AssignLocalErrorIds();
foreach (VerilogModuleInstance vmi in root.InstantiatedModules)
{
PopulateDisplayHeirarchy(display.Nodes[0], vmi.Type);
}
}
/// <summary>
/// Inserts all the inputs and outputs into the module being shadowed that are required by the shadow capture module
/// </summary>
/// <param name="vMod"></param>
/// <param name="changeLog"></param>
private void InsertLocalPorts(InserterMode mode, VerilogModule vMod, FileChangeLog changeLog)
{
StringBuilder inouts = new StringBuilder(Environment.NewLine);
if (mode == InserterMode.Error || mode == InserterMode.Both)
{
inouts.AppendLine("," + Environment.NewLine + "//*****[ERROR CAPTURE MODULE INOUTS]*****");
inouts.AppendLine("\t" + ERROR_ENABLE + ", // Error injection enable");
inouts.AppendLine("\t" + ERROR_CONTROL + " // Error injection control");
}
if (mode == InserterMode.Shadow || mode == InserterMode.Both)
{
inouts.AppendLine("," + Environment.NewLine + "//*****[SHADOW CAPTURE MODULE INOUTS]*****");
inouts.AppendLine("\t" + SHADOW_CLOCK + ", // Shadow/data clock");
inouts.AppendLine("\t" + SHADOW_RESET + ", // Shadow/data reset");
inouts.AppendLine("\t" + CAPTURE_ENABLE + ", // Capture enable");
inouts.AppendLine("\t" + DUMP_ENABLE + ", // Dump enable");
inouts.AppendLine("\t" + CHAINS_OUT + ", // Chains out");
inouts.AppendLine("\t" + CHAINS_OUT_VALID + ", // Chains out valid");
inouts.AppendLine("\t" + CHAINS_OUT_DONE + " // Chains done");
}
changeLog.ProposeChange(vMod.InOutListEnd.Pos, inouts.ToString());
StringBuilder inoutDeclarations = new StringBuilder(Environment.NewLine);
if ((mode == InserterMode.Error || mode == InserterMode.Both) && vMod.ErrorControlWidth > 0)
{
inoutDeclarations.AppendLine("parameter " + ERROR_PARAMETER + " = 1;" + Environment.NewLine);
inoutDeclarations.AppendLine("\t//*****[ERROR CAPTURE MODULE INOUTS INSTANTIATIONS]*****");
inoutDeclarations.AppendLine("\tinput\t" + ERROR_ENABLE + "; // Error injection enable");
inoutDeclarations.AppendLine("\tinput\t" + ((vMod.ErrorControlWidth == 1) ? string.Empty : "[" + (vMod.ErrorControlWidth - 1) + ":0] ") + ERROR_CONTROL + "; // Error injection control");
inoutDeclarations.AppendLine("");
}
if (mode == InserterMode.Shadow || mode == InserterMode.Both)
{
string chainsOutLimits = "[" + (vMod.NumChainsOut - 1) + ":0]";
inoutDeclarations.AppendLine("\t//*****[SHADOW CAPTURE MODULE INOUT INSTANTIATIONS]*****");
inoutDeclarations.AppendLine("\tinput\t" + SHADOW_CLOCK + "; // Shadow/data clock");
inoutDeclarations.AppendLine("\tinput\t" + SHADOW_RESET + "; // Shadow/data reset");
inoutDeclarations.AppendLine("\tinput\t" + CAPTURE_ENABLE + "; // Capture enable");
inoutDeclarations.AppendLine("\tinput\t" + chainsOutLimits + "\t" + DUMP_ENABLE + "; // Dump enable");
inoutDeclarations.AppendLine("\toutput\t" + chainsOutLimits + "\t" + CHAINS_OUT + "; // Chains out");
inoutDeclarations.AppendLine("\toutput\t" + chainsOutLimits + "\t" + CHAINS_OUT_VALID + "; // Chains out Valid");
inoutDeclarations.AppendLine("\toutput\t" + chainsOutLimits + "\t" + CHAINS_OUT_DONE + "; // Chains done");
}
changeLog.ProposeChange(vMod.PostHeader.Pos, inoutDeclarations.ToString());
}
/// <summary>
/// Replaces all PossibleInstances with real instances of the VerilogModule type.
/// Used after the type has been found.
/// </summary>
/// <param name="vMod"></param>
public void ReplacePossibleInstances(VerilogModule vMod)
{
if (!this.possibleInstances.ContainsKey(vMod.Name))
{
return;
}
List <PossibleInstance> lpi = this.possibleInstances[vMod.Name];
foreach (PossibleInstance pInst in lpi)
{
VerilogModuleInstance vmi = new VerilogModuleInstance(pInst.ParentModule, vMod, pInst.InstanceName, pInst.InOutListEnd);
vmi.Parameterized = pInst.paramsExist;
vmi.ParametersNamed = pInst.paramsNamed;
vmi.ParameterList = pInst.paramList;
this.moduleInstances.Add(vmi);
}
this.possibleInstances.Remove(vMod.Name);
}
//private string RouteDataClocks(VerilogModule vMod) {
// if (vMod.LocalDffs.Count == 0)
// return string.Empty;
// StringBuilder dataClocks = new StringBuilder("{");
// for (int i = 0; i < vMod.LocalDffs.Count; i++) {
// //if (vMod.LocalDffs[i].Size != 1) {
// // dataClocks.Append("{" + vMod.LocalDffs[i].Size + "{" + vMod.LocalDffs[i].ClockPort + "}}");
// //} else {
// dataClocks.Append(vMod.LocalDffs[i].ClockPort);
// //}
// if (i != vMod.LocalDffs.Count - 1)
// dataClocks.Append(", ");
// }
// dataClocks.Append("}");
// return dataClocks.ToString();
//}
/// <summary>
/// Returns a string of all the outputs of the local DFFs
/// </summary>
/// <param name="vMod"></param>
/// <returns></returns>
private string RouteLocalDffs(VerilogModule vMod)
{
if (vMod.LocalDffs.Count == 0)
{
return(string.Empty);
}
StringBuilder dffOutputs = new StringBuilder("{");
for (int i = 0; i < vMod.LocalDffs.Count; i++)
{
dffOutputs.Append(vMod.LocalDffs[i].QPort);
if (i != vMod.LocalDffs.Count - 1)
{
dffOutputs.Append(", ");
}
}
dffOutputs.Append("}");
return(dffOutputs.ToString());
}
/// <summary>
/// Returns a string of all the shadow outputs of the instantiated modules
/// </summary>
/// <param name="vMod"></param>
/// <param name="changeLog"></param>
/// <returns></returns>
private string RouteInstanceShadowChains(VerilogModule vMod)
{
if (vMod.NumChainsIn == 0)
{
return(string.Empty);
}
// TODO: Change to dynamic number of chains out
/*
* StringBuilder shadowChains = new StringBuilder("{");
* for (int i = 0; i < vMod.InstantiatedModules.Count; i++) {
* shadowChains.Append("ch_out_" + vMod.InstantiatedModules[i].InstanceName);
* if (i != vMod.InstantiatedModules.Count - 1)
* shadowChains.Append(", ");
* }
* shadowChains.Append("}");
* return shadowChains.ToString();*/
return(INST_CHAINS_OUT);
}
/// <summary>
/// Instantiates all wires required for routing signals to/from the shadow capture module
/// </summary>
/// <param name="vMod"></param>
/// <param name="changeLog"></param>
private void InstantiateWires(InserterMode mode, VerilogModule vMod, FileChangeLog changeLog)
{
StringBuilder wireInst = new StringBuilder(Environment.NewLine);
if (mode == InserterMode.Error || mode == InserterMode.Both)
{
wireInst.AppendLine("\t//*****[ERROR WIRE INSTANTIATIONS]******");
if (vMod.NumLocalDffs > 0)
{
wireInst.AppendLine("\twire [" + (vMod.NumLocalDffs - 1) + ":0] " + ERROR_LOCAL_CONTROL + ";");
}
foreach (VerilogModuleInstance vmi in vMod.InstantiatedModules)
{
if (vmi.Type.ErrorControlWidth <= 0)
{
continue;
}
wireInst.AppendLine("\twire " + vmi.InstanceName + "_" + ERROR_ENABLE + ";");
wireInst.AppendLine("\twire " + ((vmi.Type.ErrorControlWidth == 0)? string.Empty : "[" + (vmi.Type.ErrorControlWidth - 1) + ":0] ") + vmi.InstanceName + "_" + ERROR_CONTROL + ";");
}
changeLog.ProposeChange(vMod.PostHeader.Pos, wireInst.ToString());
wireInst.Clear();
}
if (mode == InserterMode.Shadow || mode == InserterMode.Both)
{
if (vMod.NumChainsIn == 0)
{
return;
}
string bitLimits = (vMod.NumChainsIn == 1) ? string.Empty : "[" + (vMod.NumChainsIn - 1).ToString() + ":0] ";
wireInst.AppendLine(Environment.NewLine + "//*****[SHADOW WIRE INSTANTIATIONS]*****");
wireInst.AppendLine("\twire " + bitLimits + INST_CHAINS_OUT + ";");
wireInst.AppendLine("\twire " + bitLimits + INST_CHAINS_OUT_VALID + ";");
wireInst.AppendLine("\twire " + bitLimits + INST_CHAINS_OUT_DONE + ";");
wireInst.AppendLine("\twire " + bitLimits + CHAINS_DUMP_ENABLE + ";");
wireInst.AppendLine("");
changeLog.ProposeChange(vMod.PostHeader.Pos, wireInst.ToString());
}
}
private void InstantiateLocalErrorSplitter(VerilogModule vMod, FileChangeLog changeLog)
{
if (vMod.NumLocalDffs == 0)
{
return;
}
StringBuilder lesSB = new StringBuilder(Environment.NewLine);
lesSB.AppendLine("\t//[Local Error Control Splitter Instantiation here]");
lesSB.AppendLine("\tlclErrCtrlSplitter #(.INW(" + vMod.ErrorControlWidth +
"), .LCL(" + vMod.NumLocalDffs + ")) " +
ERROR_LCL_MOD_NAME + "_" + vMod.Name + "(");
lesSB.AppendLine("\t\t.err_en(err_en),");
lesSB.AppendLine("\t\t.err_ctrl(err_ctrl),");
lesSB.AppendLine("\t\t.lcl_err(lcl_err)");
lesSB.AppendLine("\t);");
lesSB.AppendLine(Environment.NewLine);
changeLog.ProposeChange(vMod.PrevEndModule.Pos, lesSB.ToString());
}
public void AddModuleToLibrary(VerilogModule module)
{
this.moduleLibrary.Add(module.Name, module);
}
public string GetWorkingCopyPath(VerilogModule vMod)
{
return(System.IO.Path.Combine(projectDirectory, System.IO.Path.GetFileName(vMod.Filename)));
}
public VerilogModuleTreeNode(VerilogModule moduleType)
{
this.node = new TreeNode(moduleType.Name);
this.moduleType = moduleType;
}
private VerilogModule ParseModuleDeclaration(StringTokenizer tknzr, VerilogFile vFile)
{
#region Are the ports even needed? Besides knowing where to insert the shadow chain ports
/*
* List<string> inPorts = new List<string>();
* List<string> outPorts = new List<string>();
* List<string> inoutPorts = new List<string>();
* Token currToken = null;
* Token prevToken = new Token(TokenKind.Unknown, "", 0, 0, 0);
* while (true) {
* if (currToken == null) {
* tknzr.Next();
* }
* currToken = tknzr.Next();
* if (currToken.Kind == TokenKind.EOF) {
* break;
* } else if (currToken.Value == ";" && prevToken.Value == ")") {
* break;
* } else if (currToken.Value == "input" && prevToken.Kind == TokenKind.EOL) {
*
* }
* prevToken = currToken;
* }
*/
#endregion
Token prevTok = tknzr.Next();
Token twoPrevTok = prevTok;
Token currTok = tknzr.Next();
VerilogModule vMod = new VerilogModule(vFile.FileName, prevTok.Value);
bool headerParsed = false;
while (currTok.Value != "endmodule" && currTok.Kind != TokenKind.EOF)
{
if (prevTok.Kind == TokenKind.EOL)
{
if (!RunPrecompiler(tknzr, ref prevTok, ref currTok))
{
if (currTok.Value == "parameter")
{
// PARAMETER FOUND
ParseParameter(tknzr, vMod.Parameters);
}
else if (this.project.IsDff(currTok.Value))
{
// DFF INSTANCE FOUND
DffInstance dffInst = ParseDffInstance(tknzr, currTok, project.GetDffType(currTok.Value));
if (dffInst == null)
{
throw new InvalidDataException("DFF Library was unable to instantiate from type retrieved from project.");
}
vMod.AddDffInstance(dffInst);
}
else if (this.project.IsModule(currTok.Value))
{
// MODULE INSTANCE FOUND
VerilogModuleInstance vModInst = ParseModuleInstance(vMod, tknzr, currTok, project.GetModule(currTok.Value));
if (vModInst == null)
{
throw new InvalidDataException("Error instantiating module from type retrieved from project.");
}
vMod.AddModuleInstance(vModInst);
}
else if (headerParsed && !this.project.IsKeyword(currTok.Value) && currTok.Kind == TokenKind.Word)
{
// POSSIBLE MODULE, NOT YET PARSED
/* OPTIMZATION:
* TODO: Change tokenizer to ignore everything between certain keywords and ';',
* EX: "assign blah = blah blah blah;" in case there is weird indenting for
* readibility. This will minimize the number of false Possibles.
* */
if (currTok.Value == "lsu_dc_parity_gen")
{
Console.Write("!");
}
StringTokenizer tempTknzr = new StringTokenizer(tknzr); // Perform deep copy to leave tknzr untouched
Token nameTok = tempTknzr.Next();
bool paramExist = false;
bool paramNamed = false;
Token paramList = null;
/*if (nameTok.Value == "#") {
* paramsExist = true;
* tempTknzr.Next();// (
* tempTknzr.Next();// Number
* tempTknzr.Next();// )
* nameTok = tempTknzr.Next();
* }*/
if (nameTok.Value == "#")
{
// Run through parameter lists until parens all closed
paramExist = true;
paramList = tempTknzr.Next(); // after "#("
if (paramList.Value == "(")
{
int parenPairs = 1;
while (parenPairs > 0)
{
nameTok = tempTknzr.Next();
if (nameTok.Value.Contains("."))
{
paramNamed = true;
}
if (nameTok.Value == "(")
{
parenPairs++;
}
else if (nameTok.Value == ")")
{
parenPairs--;
}
}
}
nameTok = tempTknzr.Next();
}
else
{
paramList = currTok;
}
Token tempCurrTok = tempTknzr.Next();
Token tempPrevTok = tempCurrTok;
Token tempTwoPrevTok = tempCurrTok;
while (tempCurrTok.Value != ";")
{
// Run through in/out list to end of instantiation
tempTwoPrevTok = tempPrevTok; // At ')'
tempPrevTok = tempCurrTok; // At ';'
tempCurrTok = tempTknzr.Next(); // After ';'
}
vMod.AddPossibleInstance(currTok, nameTok.Value, tempTwoPrevTok, paramExist, paramNamed, paramList);
}
}
}
twoPrevTok = prevTok;
prevTok = currTok;
currTok = tknzr.Next();
if (!headerParsed && currTok.Value == ";" /*&& prevTok.Value == ")"*/)
{
vMod.InOutListEnd = twoPrevTok;
vMod.PostHeader = tknzr.Next();
twoPrevTok = prevTok;
prevTok = (currTok.Value == ")")? currTok : prevTok;
currTok = vMod.PostHeader;
headerParsed = true;
}
}
vMod.PrevEndModule = prevTok;
return(vMod);
}
public VerilogModuleInstance ParseModuleInstance(VerilogModule parent, StringTokenizer tknzr, Token possibleParamList, VerilogModule modInstType)
{
string instName;
Token paramListBegin = possibleParamList;//tknzr.Next();
bool paramExists = false;
bool paramsNamed = false;
string word = tknzr.Next().Value;
if (word == "#")
{
// Run through parameter lists until parens all closed
paramExists = true;
//paramListBegin =
tknzr.Next(); // after "#("
int parenPairs = 1;
while (parenPairs > 0)
{
word = tknzr.Next().Value;
if (word.Contains("."))
{
paramsNamed = true;
}
if (word == "(")
{
parenPairs++;
}
else if (word == ")")
{
parenPairs--;
}
}
instName = tknzr.Next().Value;
}
else
{
instName = word;
}
if (instName.Contains("st4_rrobin") || parent.Name == "lsu_rrobin_picker2")
{
Console.Write("pOOp");
}
Token currTok = tknzr.Next();
Token prevTok = currTok;
Token twoPrevTok = currTok;
while (currTok.Value != ";")
{
// Run through in/out list to end of instantiation
twoPrevTok = prevTok; // At ')'
prevTok = currTok; // At ';'
currTok = tknzr.Next(); // After ';'
}
VerilogModuleInstance vModInst = modInstType.Instantiate(parent, instName, twoPrevTok);
vModInst.ParameterList = paramListBegin;
vModInst.Parameterized = paramExists;
vModInst.ParametersNamed = paramsNamed;
return(vModInst);
}
public VerilogModuleInstance Instantiate(VerilogModule parent, string name, Token inoutListEnd)
{
return(new VerilogModuleInstance(parent, this, name, inoutListEnd));
}
