private void WritePort(ushort port, byte value)
{
port &= 0xFF;
if (port >= 0xA0 && port <= 0xBF)
{
if ((port & 1) == 0)
{
VDP.WriteVdpData(value);
}
else
{
VDP.WriteVdpControl(value);
}
return;
}
if (port >= 0x80 && port <= 0x9F)
{
InputPortSelection = InputPortMode.Right;
return;
}
if (port >= 0xC0 && port <= 0xDF)
{
InputPortSelection = InputPortMode.Left;
return;
}
if (port >= 0xE0)
{
PSG.WritePsgData(value, Cpu.TotalExecutedCycles);
return;
}
}
public void WriteMemoryZ80(ushort address, byte value)
{
if (address < 0x4000)
{
//Console.WriteLine("write z80 memory {0:X4}: {1:X2}",address, value);
Z80Ram[address & 0x1FFF] = value;
return;
}
if (address >= 0x4000 && address < 0x6000)
{
//Console.WriteLine(" === Z80 WRITES YM2612 {0:X4}:{1:X2} ===",address, value);
YM2612.Write(address & 3, value, SoundCPU.TotalExecutedCycles);
return;
}
if (address < 0x6100)
{
BankRegion >>= 1;
BankRegion |= (value & 1) << 23;
BankRegion &= 0x00FF8000;
//Console.WriteLine("Bank pointing at {0:X8}",BankRegion);
return;
}
if (address >= 0x7F00 && address < 0x7F20)
{
switch (address & 0x1F)
{
case 0x00:
case 0x02:
VDP.WriteVdpData((ushort)((value << 8) | value));
return;
case 0x04:
case 0x06:
VDP.WriteVdpControl((ushort)((value << 8) | value));
return;
case 0x11:
case 0x13:
case 0x15:
case 0x17:
PSG.WritePsgData(value, SoundCPU.TotalExecutedCycles);
return;
}
}
if (address >= 0x8000)
{
WriteByte(BankRegion | (address & 0x7FFF), (sbyte)value);
return;
}
Console.WriteLine("UNHANDLED Z80 WRITE {0:X4}:{1:X2}", address, value);
}
public void WriteByte(int address, sbyte value)
{
address &= 0x00FFFFFF;
if (address >= 0xE00000) // Work RAM
{
//Console.WriteLine("MEM[{0:X4}] change from {1:X2} to {2:X2}", address & 0xFFFF, Ram[address & 0xFFFF], value);
Ram[address & 0xFFFF] = (byte)value;
return;
}
if ((address & 0xFF0000) == 0xA00000)
{
WriteMemoryZ80((ushort)(address & 0x7FFF), (byte)value);
return;
}
if (address >= 0xA10000 && address <= 0xA1001F)
{
WriteIO(address, value);
return;
}
if (address == 0xA11100)
{
M68000HasZ80Bus = (value & 1) != 0;
//Console.WriteLine("68000 has the z80 bus: " + M68000HasZ80Bus);
return;
}
if (address == 0xA11200) // Z80 RESET
{
Z80Reset = (value & 1) == 0;
if (Z80Reset)
{
SoundCPU.SoftReset();
}
//Console.WriteLine("z80 reset: " + Z80Reset);
return;
}
if (address >= 0xC00000 && address < 0xC00010)
{
// when writing to VDP in byte mode, the LSB is duplicated into the MSB
VDP.WriteVdp(address & 0x1E, (ushort)((ushort)value | ((ushort)value << 8)));
return;
}
if (address >= 0xC00011 && address <= 0xC00017 && (address & 1) != 0)
{
PSG.WritePsgData((byte)value, SoundCPU.TotalExecutedCycles);
return;
}
if (SaveRamEnabled && address >= SaveRamStartOffset && address < SaveRamEndOffset)
{
if (SaveRamEveryOtherByte)
{
SaveRAM[(address - SaveRamStartOffset) >> 1] = (byte)value;
}
else
{
SaveRAM[address - SaveRamStartOffset] = (byte)value;
}
SaveRamModified = true;
return;
}
if (EepromEnabled && (address == SclAddr || address == SdaInAddr))
{
WriteByteEeprom(address, (byte)value);
return;
}
Console.WriteLine("UNHANDLED WRITEB {0:X6}:{1:X2}", address, value);
}