private void m6800_reset()
{
SEI(); /* IRQ disabled */
PC.LowWord = RM16(0xfffe);
wai_state = 0;
nmi_state = 0;
irq_state[0] = 0;
irq_state[1] = 0;
ic_eddge = 0;
port1_ddr = 0x00;
port2_ddr = 0x00;
tcsr = 0x00;
pending_tcsr = 0x00;
irq2 = 0;
counter.d = 0x0000;
output_compare.d = 0xffff;
timer_over.d = 0xffff;
ram_ctrl |= 0x40;
trcsr = M6800_TRCSR_TDRE;
rmcr = 0;
Timer.timer_enable(m6800_rx_timer, false);
Timer.timer_enable(m6800_tx_timer, false);
txstate = M6800_TX_STATE.INIT;
txbits = rxbits = 0;
trcsr_read = 0;
}
public void m6800_tx_tick()
{
if ((trcsr & M6800_TRCSR_TE) != 0)
{
port2_ddr |= M6800_PORT2_IO4;
switch (txstate)
{
case M6800_TX_STATE.INIT:
tx = 1;
txbits++;
if (txbits == 10)
{
txstate = M6800_TX_STATE.READY;
txbits = 0;
}
break;
case M6800_TX_STATE.READY:
switch (txbits)
{
case 0:
if ((trcsr & M6800_TRCSR_TDRE) != 0)
{
tx = 1;
}
else
{
tsr = tdr;
trcsr |= M6800_TRCSR_TDRE;
tx = 0;
txbits++;
}
break;
case 9:
// send stop bit '1'
tx = 1;
CHECK_IRQ_LINES();
txbits = 0;
break;
default:
tx = tsr & 0x01;
tsr >>= 1;
txbits++;
break;
}
break;
}
}
m6800_tx(tx);
}
private void m6803_internal_registers_w(int offset, byte data)
{
int latch09 = 0;
switch (offset)
{
case 0x00:
if (port1_ddr != data)
{
port1_ddr = data;
if (port1_ddr == 0xff)
{
WriteIO(0x100, port1_data);
}
else
{
WriteIO(0x100, (byte)((port1_data & port1_ddr) | (ReadIO(0x100) & (port1_ddr ^ 0xff))));
}
}
break;
case 0x01:
if (port2_ddr != data)
{
port2_ddr = data;
if (port2_ddr == 0xff)
{
WriteIO(0x101, port2_data);
}
else
{
WriteIO(0x101, (byte)((port2_data & port2_ddr) | (ReadIO(0x101) & (port2_ddr ^ 0xff))));
}
if ((port2_ddr & 2) != 0)
{
//logerror("CPU #%d PC %04x: warning - port 2 bit 1 set as output (OLVL) - not supported\n", cpu_getactivecpu(), activecpu_get_pc());
}
}
break;
case 0x02:
port1_data = data;
if (port1_ddr == 0xff)
{
WriteIO(0x100, port1_data);
}
else
{
WriteIO(0x100, (byte)((port1_data & port1_ddr) | (ReadIO(0x100) & (port1_ddr ^ 0xff))));
}
break;
case 0x03:
if ((trcsr & M6800_TRCSR_TE) != 0)
{
port2_data = (byte)((data & 0xef) | (tx << 4));
}
else
{
port2_data = data;
}
if (port2_ddr == 0xff)
{
WriteIO(0x101, port2_data);
}
else
{
WriteIO(0x101, (byte)((port2_data & port2_ddr) | (ReadIO(0x101) & (port2_ddr ^ 0xff))));
}
break;
case 0x04:
if (port3_ddr != data)
{
port3_ddr = data;
if (port3_ddr == 0xff)
{
WriteIO(0x102, port3_data);
}
else
{
WriteIO(0x102, (byte)((port3_data & port3_ddr) | (ReadIO(0x102) & (port3_ddr ^ 0xff))));
}
}
break;
case 0x05:
if (port4_ddr != data)
{
port4_ddr = data;
if (port4_ddr == 0xff)
{
WriteIO(0x103, port4_data);
}
else
{
WriteIO(0x103, (byte)((port4_data & port4_ddr) | (ReadIO(0x103) & (port4_ddr ^ 0xff))));
}
}
break;
case 0x06:
port3_data = data;
if (port3_ddr == 0xff)
{
WriteIO(0x102, port3_data);
}
else
{
WriteIO(0x102, (byte)((port3_data & port3_ddr) | (ReadIO(0x102) & (port3_ddr ^ 0xff))));
}
break;
case 0x07:
port4_data = data;
if (port4_ddr == 0xff)
{
WriteIO(0x103, port4_data);
}
else
{
WriteIO(0x103, (byte)((port4_data & port4_ddr) | (ReadIO(0x103) & (port4_ddr ^ 0xff))));
}
break;
case 0x08:
tcsr = data;
pending_tcsr &= tcsr;
MODIFIED_tcsr();
if ((cc & 0x10) == 0)
{
m6800_check_irq2();
}
break;
case 0x09:
latch09 = data & 0xff; /* 6301 only */
counter.LowWord = 0xfff8;
timer_over.LowWord = counter.HighWord;
MODIFIED_counters();
break;
case 0x0a: /* 6301 only */
counter.LowWord = (ushort)((latch09 << 8) | (data & 0xff));
timer_over.LowWord = counter.HighWord;
MODIFIED_counters();
break;
case 0x0b:
if (output_compare.HighByte != data)
{
output_compare.HighByte = data;
MODIFIED_counters();
}
break;
case 0x0c:
if (output_compare.LowByte != data)
{
output_compare.LowByte = data;
MODIFIED_counters();
}
break;
case 0x0d:
case 0x0e:
case 0x12:
//logerror("CPU #%d PC %04x: warning - write %02x to read only internal register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),data,offset);
break;
case 0x0f:
//logerror("CPU #%d PC %04x: warning - write %02x to unsupported internal register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),data,offset);
break;
case 0x10:
rmcr = (byte)(data & 0x0f);
switch ((rmcr & M6800_RMCR_CC_MASK) >> 2)
{
case 0:
case 3: // not implemented
Timer.timer_enable(m6800_rx_timer, false);
Timer.timer_enable(m6800_tx_timer, false);
break;
case 1:
case 2:
{
int divisor = M6800_RMCR_SS[rmcr & M6800_RMCR_SS_MASK];
Timer.timer_adjust_periodic(m6800_rx_timer, Attotime.ATTOTIME_ZERO, new Atime(0, (long)(1e18 / (clock / divisor))));
Timer.timer_adjust_periodic(m6800_tx_timer, Attotime.ATTOTIME_ZERO, new Atime(0, (long)(1e18 / (clock / divisor))));
}
break;
}
break;
case 0x11:
if ((data & M6800_TRCSR_TE) != 0 && (trcsr & M6800_TRCSR_TE) == 0)
{
txstate = 0;
}
trcsr = (byte)((trcsr & 0xe0) | (data & 0x1f));
break;
case 0x13:
if (trcsr_read != 0)
{
trcsr_read = (int)M6800_TX_STATE.INIT;
trcsr &= (byte)(~M6800_TRCSR_TDRE);
}
tdr = data;
break;
case 0x14:
//logerror("CPU #%d PC %04x: write %02x to RAM control register\n",cpu_getactivecpu(),activecpu_get_pc(),data);
ram_ctrl = data;
break;
case 0x15:
case 0x16:
case 0x17:
case 0x18:
case 0x19:
case 0x1a:
case 0x1b:
case 0x1c:
case 0x1d:
case 0x1e:
case 0x1f:
default:
//logerror("CPU #%d PC %04x: warning - write %02x to reserved internal register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),data,offset);
break;
}
}
