public static void Transform(uint bits, ComplexFloat[] data, Direction direction)
{
FPGA.Const <uint> n = GeneratorTools.ArrayLength(bits);
FPGA.Const <float> nFloat = GeneratorTools.FloatArrayLength(bits);
uint mask = GeneratorTools.Mask(bits);
ComplexFloat[] transformed = new ComplexFloat[data.Length];
float[] cosMap = GeneratorTools.CosArray(n, direction);
var tmp = new ComplexFloat();
// for each destination element
for (uint i = 0; i < n; i++)
{
tmp.Re = 0.0f;
tmp.Im = 0.0f;
// sum source elements
for (uint j = 0; j < n; j++)
{
ComplexFloat source = new ComplexFloat();
source = data[j];
FTTools.RotateAndAdd(cosMap, bits, ref source, ref tmp, i * j);
}
transformed[i] = tmp;
}
FTTools.CopyAndNormalize(bits, transformed, data, direction, ref tmp);
}
// module has one non-registered input bit, and one registered output byte
public static byte Read(uint baud, FPGA.InputSignal <bool> RXD)
{
FPGA.Const <ulong> delay = 1000000000 / baud;
byte result = 0;
// all combinational logic is expressed as delegates
Func <bool> invertedRXD = () => !RXD;
// wait for start bit
FPGA.Runtime.WaitForAllConditions(invertedRXD);
// wait for half bit time to allow some time shift errors
FPGA.Runtime.Delay(delay / 2);
// read 8 bits
for (uint i = 0; i < 8; i++)
{
FPGA.Config.SetInclusiveRange(0, 8, i);
FPGA.Runtime.Delay(delay);
// this is assign of combinational expression
// evaluated and assigned during single clock cycle
result = (byte)((result >> 1) | ((byte)RXD << 7));
}
// stop bit
FPGA.Runtime.Delay(delay);
return(result);
}
public static void RotateAndAdd(
float[] cosMap,
uint bits,
ref ComplexFloat source,
ref ComplexFloat target,
uint arg)
{
FPGA.Const <uint> mask = GeneratorTools.Mask(bits);
if (bits == 0)
{
target.Re = source.Re;
target.Im = source.Im;
}
else
{
float cos = 0.0f, sin = 0.0f;
uint cosIdx = arg & mask;
cos = cosMap[cosIdx];
if (bits > 1)
{
uint sinIdx = (uint)(cosIdx + (cosMap.Length >> 2)) & mask;
sin = cosMap[sinIdx];
}
target.Re += source.Re * cos - source.Im * sin;
target.Im += source.Re * sin + source.Im * cos;
}
}
static void internalFPUCastSync()
{
FPGA.Const <bool> floatToIntCastSync = true;
object floatToIntCastLock = new object();
FPGA.Const <bool> intToFloatCastSync = true;
object intToFloatCastLock = new object();
}
public static void RegisteredWrite(uint baud, byte data, out bool TXD)
{
FPGA.Const <ulong> delay = 1000000000 / baud;
byte stored = data;
// start bit
TXD = false;
FPGA.Runtime.Delay(delay);
// write data bits
for (byte i = 0; i < 8; i++)
{
FPGA.Config.SetInclusiveRange(0, 8, i);
TXD = (stored & 1) > 0;
FPGA.Runtime.Delay(delay);
stored = (byte)(stored >> 1);
}
// stop bit
TXD = true;
FPGA.Runtime.Delay(delay);
FPGA.Runtime.Delay(delay);
}
public static void CopyAndNormalize(
uint bits,
ComplexFloat[] source,
ComplexFloat[] target,
Direction direction,
ref ComplexFloat tmpBuff)
{
FPGA.Const <float> nFloat = GeneratorTools.FloatArrayLength(bits);
for (uint i = 0; i < source.Length; i++)
{
FPGA.Config.SetInclusiveRange(0, source.Length, i);
tmpBuff = source[i];
if (direction == Direction.Forward)
{
tmpBuff.Re = tmpBuff.Re / nFloat;
tmpBuff.Im = tmpBuff.Im / nFloat;
}
target[i] = tmpBuff;
}
}
static void internalFPUOpSync()
{
object fpuLock = new object();
FPGA.Const <bool> fpuSync = true;
}
public static void Transform(
uint bits,
ComplexFloat[] source,
ComplexFloat[] target,
Direction direction)
{
FPGA.Const <uint> length = GeneratorTools.ArrayLength(bits);
float[] cosMap = GeneratorTools.CosArray(length, direction);
FPGA.Config.NoSync(cosMap, target);
var eK = new ComplexFloat();
var oK = new ComplexFloat();
var rotated = new ComplexFloat();
var tmp = new ComplexFloat();
for (uint i = 0; i < source.Length; i++)
{
uint j = FPGA.Runtime.Reverse(i, bits);
tmp = source[i];
target[j] = tmp;
}
uint m = 1;
uint groupSize = length;
for (uint i = 0; i < bits; i++)
{
FPGA.Config.SetInclusiveRange(0, bits, i);
groupSize = groupSize >> 1;
for (uint group = 0; group < m; group++)
{
FPGA.Config.SetInclusiveRange(0, bits, i);
uint arg = groupSize * group;
for (uint idx = group; idx < length; idx += m * 2)
{
FPGA.Config.SetInclusiveRange(0, bits, i);
eK = target[idx];
oK = target[idx + m];
FTTools.Rotate(cosMap, bits, ref oK, ref rotated, arg);
tmp.Re = eK.Re + rotated.Re;
tmp.Im = eK.Im + rotated.Im;
target[idx] = tmp;
tmp.Re = eK.Re - rotated.Re;
tmp.Im = eK.Im - rotated.Im;
target[idx + m] = tmp;
}
}
m = m << 1;
}
FTTools.CopyAndNormalize(bits, target, target, direction, ref tmp);
}
