public static void RunTest()
{
DesignContext.Reset();
TestHLS_CordicSqrt_Testbench tb = new TestHLS_CordicSqrt_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(100.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
var docproj = new DocumentationProject(@".\hdl_out_TestHLSSqrt_Cordic\doc");
var project = new XilinxProject(@".\hdl_out_TestHLSSqrt_Cordic", "TestHLSSqrt_Cordic");
project.ISEVersion = EISEVersion._13_2;
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
//project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
SynthesisEngine.Create(DesignContext.Instance, docproj).Synthesize(new DocumentationGenerator());
project.Save();
docproj.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_PortAccess_Testbench tb = new TestHLS_PortAccess_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
DesignContext.Stop();
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_PortAccess", "TestHLS_PortAccess");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_CFlow2_Testbench tb = new TestHLS_CFlow2_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(100.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX75T_FF484 fpga = new XC6VLX75T_FF484()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = tb.DUT
};
fpga.Testbenches.Add(tb);
fpga.Synthesize(@".\hdl_out_TestHLS_CFlow2", "TestHLS_CFlow2");
var eng = SynthesisEngine.Create(
DesignContext.Instance, new DocumentationProject(@".\hdl_out_TestHLS_CFlow2\doc"));
eng.Synthesize(new DocumentationGenerator());
}
public static void RunTest()
{
DesignContext.Reset();
FixedPointSettings.GlobalDefaultRadix = 10;
var tb = new Test_SinCosLUT_Testbench(7, 8, 9, 0);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
DesignContext.Stop();
//XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_Test_SinCosLUT_Testbench", "Test_SinCosLUT_Testbench");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
project.TwinProject = new ModelsimProject(@".\hdl_out_Test_SinCosLUT_Testbench", "Test_SinCosLUT_Testbench");
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
}
private async void Process()
{
System.Threading.Thread.CurrentThread.CurrentCulture = System.Globalization.CultureInfo.InvariantCulture;
do
{
await RisingEdge(CLK);
}while (!data_ready.Cur && !data_fin.Cur);
if (data_fin.Cur)
{
DesignContext.Stop();
}
_tw_real.Write(in_real.Cur);
_tw_real.WriteLine();
_tw_imag.Write(in_imag.Cur);
_tw_imag.WriteLine();
data_ack.Next = true;
do
{
await RisingEdge(CLK);
}while (data_ready.Cur);
data_ack.Next = false;
}