public static void RunTest()
{
DesignContext.Reset();
Testbench tb = new Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(101 * Testbench.ClockPeriod);
DesignContext.Instance.CompleteAnalysis();
VHDLGenerator codeGen = new VHDLGenerator();
DocumentationProject proj = new DocumentationProject("./doc");
SynthesisEngine.Create(DesignContext.Instance, proj).Synthesize(codeGen);
proj.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_CordicSqrt_Testbench tb = new TestHLS_CordicSqrt_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(100.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
var docproj = new DocumentationProject(@".\hdl_out_TestHLSSqrt_Cordic\doc");
var project = new XilinxProject(@".\hdl_out_TestHLSSqrt_Cordic", "TestHLSSqrt_Cordic");
project.ISEVersion = EISEVersion._13_2;
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
//project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
SynthesisEngine.Create(DesignContext.Instance, docproj).Synthesize(new DocumentationGenerator());
project.Save();
docproj.Save();
}
