/* * /// <summary> * /// Return tiles along with the ports to block on their original positions * /// </summary> * /// <returns></returns> * public IEnumerable<Tuple<Tile, List<String>>> GetPortsToBlock() * { * foreach (Tile macroTile in this.m_portsToBlock.Keys) * { * yield return new Tuple<Tile, List<String>>(macroTile, this.m_portsToBlock[macroTile]); * } * } */ /// <summary> /// Return tiles along with the ports to block in the relocated positions /// </summary> /// <returns></returns> public IEnumerable <Tuple <Tile, List <FPGA.Port> > > GetPortsToBlock(Tile anchor) { if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.ISE) { foreach (Tile tileAtOriginalPosition in m_portsToBlock.Keys) { string targetLocation = ""; bool success = GetTargetLocation(tileAtOriginalPosition.Location, anchor, out targetLocation); if (success) { Tile targetTile = FPGA.FPGA.Instance.GetTile(targetLocation); // adapt port names after relocation List <Port> portsToBlock = new List <Port>(); foreach (string p in m_portsToBlock[tileAtOriginalPosition]) { string resolvedPortName = p; bool relocationSuccess = FPGATypes.ResolveLMIdentifier(resolvedPortName, str => !targetTile.SwitchMatrix.Contains(str), out resolvedPortName); if (!relocationSuccess) { throw new ArgumentException("Error during relocation: Can not relocate " + resolvedPortName + " to its new position from anchor " + anchor.Location); } portsToBlock.Add(new Port(resolvedPortName)); } yield return(new Tuple <Tile, List <Port> >(targetTile, portsToBlock)); } else { success = GetTargetLocation(tileAtOriginalPosition.Location, anchor, out targetLocation); throw new ArgumentException("Error during relocation: Can not relocate " + tileAtOriginalPosition.Location + " to its new position from anchor " + anchor.Location); } } } else if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.Vivado) { if (!IdentifierManager.Instance.IsMatch(anchor.Location, IdentifierManager.RegexTypes.CLB)) { throw new ArgumentException("Error during relocation: Can only place on CLBs"); } Tile interconnect = FPGATypes.GetInterconnectTile(anchor); Tile clbKey = m_portsToBlock.Keys.FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)); Tile intKey = m_portsToBlock.Keys.FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.Interconnect)); if (clbKey != null) { Tuple <Tile, List <Port> > clbResult = new Tuple <Tile, List <Port> >(anchor, new List <Port>()); m_portsToBlock[clbKey].ForEach(s => clbResult.Item2.Add(new Port(s))); yield return(clbResult); } if (intKey != null) { Tuple <Tile, List <Port> > intResult = new Tuple <Tile, List <Port> >(interconnect, new List <Port>()); m_portsToBlock[intKey].ForEach(s => intResult.Item2.Add(new Port(s))); yield return(intResult); } } }