protected override void DoCommandAction()
{
if (!TileSelectionManager.Instance.UserSelectionTypes.Any(s => s.Equals(UserSelectionType)))
{
throw new ArgumentException("UserSelectionType " + UserSelectionType + " does not exist");
}
List <Tile> expansion = new List <Tile>();
foreach (Tile clb in TileSelectionManager.Instance.GetSelectedTiles().Where(t =>
IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)))
{
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
Port port = interconnect.SwitchMatrix.GetDrivenPorts().FirstOrDefault(p => p.Name.Equals(Begin));
bool startIsUserSelected = TileSelectionManager.Instance.IsUserSelected(interconnect.TileKey, UserSelectionType);
bool continuePath = true;
do
{
expansion.Add(interconnect);
Location loc = Navigator.GetDestinations(interconnect, port).FirstOrDefault(l => l.Pip.Name.Equals(End));
if (loc == null)
{
throw new ArgumentException("Can not route via " + Begin + " from " + interconnect + " to " + End);
}
interconnect = loc.Tile;
continuePath =
(startIsUserSelected && TileSelectionManager.Instance.IsUserSelected(interconnect.TileKey, UserSelectionType)) ||
(!startIsUserSelected && !TileSelectionManager.Instance.IsUserSelected(interconnect.TileKey, UserSelectionType));
} while (continuePath);
}
expansion.ForEach(t => TileSelectionManager.Instance.AddToSelection(t.TileKey, false));
}
protected override void DoCommandAction()
{
CheckParameters();
List <Tile> selectionCLB = new List <Tile>();
foreach (Tile t in TileSelectionManager.Instance.GetSelectedTiles().Where(tile =>
IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB)))
{
selectionCLB.Add(t);
}
List <Tile> selectionInt = new List <Tile>();
foreach (Tile clb in selectionCLB)
{
selectionInt.Add(FPGATypes.GetInterconnectTile(clb));
}
foreach (Tile clb in selectionCLB)
{
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
foreach (Tuple <Port, Port> t in clb.SwitchMatrix.GetAllArcs().Where(a => Regex.IsMatch(a.Item2.Name, InputPortsRegex)))
{
foreach (Wire w in interconnect.WireList.Where(w => w.PipOnOtherTile.Equals(t.Item1.Name)))
{
interconnect.BlockPort(new FPGA.Port(w.LocalPip), Tile.BlockReason.ExcludedFromBlocking);
}
}
}
}
private Tile GetCorner(string identifier, FPGATypes.Direction dir)
{
Tile tile = null;
if (FPGA.FPGA.Instance.Contains(identifier))
{
tile = FPGA.FPGA.Instance.GetTile(identifier);
}
else if (identifier.Contains("_"))
{
int split = identifier.IndexOf('_');
string prefix = identifier.Substring(0, split + 1);
string suffix = identifier.Substring(split, identifier.Length - split);
tile = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => t.Location.StartsWith(prefix) && t.Location.EndsWith(suffix));
// if we can not resolve the identifer, triggger error handling in Do
if (tile == null)
{
return(null);
}
}
else
{
return(null);
}
List <Tile> otherTiles = new List <Tile>();
otherTiles.Add(tile);
// there might be more left interconnects
if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB))
{
otherTiles.Add(FPGATypes.GetInterconnectTile(tile));
}
else if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.Interconnect))
{
foreach (Tile o in FPGATypes.GetCLTile(tile))
{
otherTiles.Add(o);
}
}
if (dir == FPGATypes.Direction.West)
{
int min = otherTiles.Min(t => t.TileKey.X);
return(otherTiles.FirstOrDefault(t => t.TileKey.X == min));
}
else if (dir == FPGATypes.Direction.East)
{
int max = otherTiles.Max(t => t.TileKey.X);
return(otherTiles.FirstOrDefault(t => t.TileKey.X == max));
}
else
{
throw new ArgumentException(GetType().Name + ".GetCorner only supports East and West");
}
}
protected override void DoCommandAction()
{
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
List <string> lutInPorts = new List <string>();
foreach (Port lutInPort in clb.SwitchMatrix.Ports.Where(p => Regex.IsMatch(p.Name, LUTInPortFilter)))
{
lutInPorts.Add(lutInPort.Name);
}
Adjacency adjacency = new Adjacency(lutInPorts, EndPortFilter, LUTOutPortFilter);
// section 1
foreach (Port endPort in interconnect.SwitchMatrix.Ports.Where(p => Regex.IsMatch(p.Name, EndPortFilter)).OrderBy(p => p.Name[p.Name.Length - 1]))
{
foreach (Port logicIn in interconnect.SwitchMatrix.GetDrivenPorts(endPort))
{
// goto CLB
foreach (Location loc in Navigator.GetDestinations(interconnect, logicIn).Where(l => l.Tile.Location.Equals(clb.Location)))
{
foreach (Port lutInPort in clb.SwitchMatrix.GetDrivenPorts(loc.Pip).Where(l => Regex.IsMatch(l.Name, LUTInPortFilter)))
{
adjacency.AddConnection(endPort.Name, lutInPort.Name);
}
}
}
}
// section 2
foreach (Port lutOutPort in clb.SwitchMatrix.Ports.Where(p => Regex.IsMatch(p.Name, LUTOutPortFilter)))
{
foreach (Port logicOut in clb.SwitchMatrix.GetDrivenPorts(lutOutPort))
{
// goto int
foreach (Location locInt in Navigator.GetDestinations(clb, logicOut).Where(l => l.Tile.Location.Equals(interconnect.Location)))
{
foreach (Port logicIn in interconnect.SwitchMatrix.GetDrivenPorts(locInt.Pip))
{
foreach (Location locClb in Navigator.GetDestinations(interconnect, logicIn).Where(l => l.Tile.Location.Equals(clb.Location)))
{
foreach (Port lutInPort in clb.SwitchMatrix.GetDrivenPorts(locClb.Pip).Where(l => Regex.IsMatch(l.Name, LUTInPortFilter)))
{
adjacency.AddConnection(lutOutPort.Name, lutInPort.Name);
}
}
}
}
}
}
OutputManager.WriteOutput(adjacency.ToString());
}
private LibraryElement GetFF(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort)
{
LibraryElement el = new LibraryElement();
el.SliceNumber = SliceNumber;
el.Name = belName;
el.PrimitiveName = BELType;
el.BEL = belName;
el.LoadCommand = ToString();
el.Containter = new NetlistContainer();
el.VHDLGenericMap = "generic map ( INIT => '0' )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// Q output
XDLPort q = new XDLPort();
q.Direction = FPGATypes.PortDirection.Out;
q.ExternalName = "Q";
q.InstanceName = "unknown";
q.SlicePort = "unknown";
el.Containter.Add(q);
List <string> inputs = new List <string>();
inputs.Add("D");
inputs.Add("C");
inputs.Add("CE");
inputs.Add("R");
foreach (string i in inputs)
{
XDLPort p = new XDLPort();
p.Direction = FPGATypes.PortDirection.In;
p.ExternalName = i;
p.InstanceName = "unknown";
p.SlicePort = "unknown";
p.ConstantValuePort = false;
el.Containter.Add(p);
}
;
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
foreach (string stopOverPortName in StopOverPorts)
{
el.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(el);
}
private LibraryElement GetLUT(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort, string initValue)
{
int lutSize = 6;
LibraryElement el = new LibraryElement();
el.SliceNumber = SliceNumber;
el.Name = belName;
el.PrimitiveName = BELType;
el.BEL = belName;
el.LoadCommand = ToString();
el.Containter = new NetlistContainer();
el.VHDLGenericMap = "generic map ( INIT => X\"" + initValue + "\" )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// one output per LUT
XDLPort outPort = new XDLPort();
outPort.Direction = FPGATypes.PortDirection.Out;
outPort.ExternalName = "O";
outPort.InstanceName = "unknown";
outPort.SlicePort = "unknown";
el.Containter.Add(outPort);
// six inputs I=..I5
for (int i = 0; i < lutSize; i++)
{
AddXDLPort(el, "I", i, FPGATypes.PortDirection.In, makeInputsConstant);
}
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
List <string> lutPortNames = new List <string>();
// see LUTRouting tab
for (int i = 1; i <= lutSize; i++)
{
lutPortNames.Add(inputPortPrefix + i);
}
foreach (string stopOverPortName in StopOverPorts)
{
el.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(el);
}
private List <Command> GetTunnelCommands(FPGATypes.InterfaceDirection direction, List <Command> placementCommands)
{
List <Command> result = new List <Command>();
// TODO make parameter?
foreach (Command placeCmd in placementCommands.Where(c => c is AddSingleInstantiationByTile))
{
AddSingleInstantiationByTile addCmd = (AddSingleInstantiationByTile)placeCmd;
Tile clb = FPGA.FPGA.Instance.GetTile(addCmd.AnchorLocation);
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
ExcludePortsFromBlockingOnTileByRegexp exclude = new ExcludePortsFromBlockingOnTileByRegexp();
exclude.CheckForExistence = false;
exclude.IncludeAllPorts = false;
exclude.Location = interconnect.Location;
if (BuildTarget == Target.Static && direction == FPGATypes.InterfaceDirection.East)
{
exclude.PortNameRegexp = "(WW2E[0|1|2|3])|(EE2B[0|1|2|3])";
}
else if (BuildTarget == Target.Static && direction == FPGATypes.InterfaceDirection.West)
{
exclude.PortNameRegexp = "(EE2E[0|1|2|3])|(WW2B[0|1|2|3])";
}
else if (BuildTarget == Target.Module && direction == FPGATypes.InterfaceDirection.East)
{
exclude.PortNameRegexp = "(EE2E[0|1|2|3])|(WW2B[0|1|2|3])";
}
else if (BuildTarget == Target.Module && direction == FPGATypes.InterfaceDirection.West)
{
exclude.PortNameRegexp = "(WW2E[0|1|2|3])|(EE2B[0|1|2|3])";
}
else
{
throw new ArgumentException("Direction " + direction + " not implemented");
}
//exclude.PortNameRegexp = "((EE)|(WW))2(B|E)[0|1|2|3]"; // the epxression parser cant handle [0-3]
if (result.Count == 0)
{
exclude.Comment = " exclude tunnel wires from blocking";
}
result.Add(exclude);
}
return(result);
}
private LibraryElement GetBEL(BELInfo info)
{
LibraryElement element = new LibraryElement
{
SliceNumber = SliceNumber,
Name = info.belName,
PrimitiveName = BELType,
BEL = info.belName,
LoadCommand = ToString(),
Containter = new XDLModule(),
VHDLGenericMap = info.type.VHDLGenericMap,
VivadoConnectionPrimitive = true
};
// Outputs
foreach (string output in info.type.outputNames)
{
element.Containter.Add(MakeXDLPort(output, FPGATypes.PortDirection.Out));
}
// Inputs
foreach (string input in info.type.inputNames)
{
element.Containter.Add(MakeXDLPort(input, FPGATypes.PortDirection.In, info.type.inputsConstantValue));
}
// Get first encountered clb ?!
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
if (info.traverseBackwards)
{
TraverseBackwards(element, clb, interconnect, info);
}
foreach (string stopOverPortName in StopOverPorts)
{
element.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(element);
}
public TileViewForm(Tile tile)
{
InitializeComponent();
m_tile = tile;
Settings.StoredPreferences.Instance.GUISettings.Open(this);
List <Tile> tiles = new List <Tile>();
tiles.Add(m_tile);
if (IdentifierManager.Instance.IsMatch(m_tile.Location, IdentifierManager.RegexTypes.Interconnect))
{
tiles.AddRange(FPGATypes.GetCLTile(m_tile));
}
if (IdentifierManager.Instance.IsMatch(m_tile.Location, IdentifierManager.RegexTypes.CLB))
{
Tile interconnect = FPGATypes.GetInterconnectTile(m_tile);
tiles.Add(interconnect);
foreach (Tile clb in FPGATypes.GetCLTile(interconnect))
{
if (!tiles.Contains(clb))
{
tiles.Add(clb);
}
}
}
foreach (Tile t in tiles)
{
TabPage page = new TabPage();
page.Text = t.Location;
TileViewCtrl viewCtrl = new TileViewCtrl(t);
viewCtrl.Dock = DockStyle.Fill;
page.Controls.Add(viewCtrl);
m_tabTop.TabPages.Add(page);
}
}
private void SelectionUpdate(SelectionUpdate selUpdate)
{
// ram drawing
if (!RAMSelectionManager.Instance.HasMappings)
{
RAMSelectionManager.Instance.UpdateMapping();
}
Graphics graphicsObj = Graphics.FromImage(TileBitmap);
switch (selUpdate.Action)
{
case (SelectionUpdateAction.AddCurrentSelectionToUserSelection):
{
foreach (Tile t in TileSelectionManager.Instance.GetUserSelection(selUpdate.UserSelectionType, m_view.TileRegex))
{
if (IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(t);
DrawTile(intTile, graphicsObj, true, true);
}
DrawTile(t, graphicsObj, true, true);
}
break;
}
case (SelectionUpdateAction.AddToSelection):
case (SelectionUpdateAction.AddToUserSelection):
{
Tile t = FPGA.FPGA.Instance.GetTile(selUpdate.AffecetedTileKey);
DrawTile(t, graphicsObj, true, true);
break;
}
case (SelectionUpdateAction.ClearAllUserSelections):
{
foreach (Tile t in TileSelectionManager.Instance.GetAllUserSelectedTiles())
{
if (IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(t);
DrawTile(intTile, graphicsObj, true, false);
}
DrawTile(t, graphicsObj, true, false);
}
break;
}
case (SelectionUpdateAction.ClearSelection):
{
foreach (Tile tile in TileSelectionManager.Instance.GetSelectedTiles().Where(t => m_view.TileRegex.IsMatch(t.Location)))
{
if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(tile);
DrawTile(intTile, graphicsObj, false, true);
}
DrawTile(tile, graphicsObj, false, true);
}
break;
}
case (SelectionUpdateAction.ClearUserSelection):
{
foreach (Tile t in TileSelectionManager.Instance.GetAllUserSelectedTiles(selUpdate.UserSelectionType))
{
if (IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(t);
DrawTile(intTile, graphicsObj, true, false);
}
DrawTile(t, graphicsObj, true, false);
}
break;
}
case (SelectionUpdateAction.RemoveFromSelection):
{
Tile t = FPGA.FPGA.Instance.GetTile(selUpdate.AffecetedTileKey);
if (IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(t);
DrawTile(intTile, graphicsObj, false, true);
}
DrawTile(t, graphicsObj, false, true);
break;
}
case (SelectionUpdateAction.InversionComplete):
{
foreach (Tile t in FPGA.FPGA.Instance.GetAllTiles())
{
DrawTile(t, graphicsObj, true, true);
}
break;
}
default:
{
throw new ArgumentException("Unexpected UpdateAction: " + selUpdate.Action);
}
}
}
/*
* /// <summary>
* /// Return tiles along with the ports to block on their original positions
* /// </summary>
* /// <returns></returns>
* public IEnumerable<Tuple<Tile, List<String>>> GetPortsToBlock()
* {
* foreach (Tile macroTile in this.m_portsToBlock.Keys)
* {
* yield return new Tuple<Tile, List<String>>(macroTile, this.m_portsToBlock[macroTile]);
* }
* }
*/
/// <summary>
/// Return tiles along with the ports to block in the relocated positions
/// </summary>
/// <returns></returns>
public IEnumerable <Tuple <Tile, List <FPGA.Port> > > GetPortsToBlock(Tile anchor)
{
if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.ISE)
{
foreach (Tile tileAtOriginalPosition in m_portsToBlock.Keys)
{
string targetLocation = "";
bool success = GetTargetLocation(tileAtOriginalPosition.Location, anchor, out targetLocation);
if (success)
{
Tile targetTile = FPGA.FPGA.Instance.GetTile(targetLocation);
// adapt port names after relocation
List <Port> portsToBlock = new List <Port>();
foreach (string p in m_portsToBlock[tileAtOriginalPosition])
{
string resolvedPortName = p;
bool relocationSuccess = FPGATypes.ResolveLMIdentifier(resolvedPortName, str => !targetTile.SwitchMatrix.Contains(str), out resolvedPortName);
if (!relocationSuccess)
{
throw new ArgumentException("Error during relocation: Can not relocate " + resolvedPortName + " to its new position from anchor " + anchor.Location);
}
portsToBlock.Add(new Port(resolvedPortName));
}
yield return(new Tuple <Tile, List <Port> >(targetTile, portsToBlock));
}
else
{
success = GetTargetLocation(tileAtOriginalPosition.Location, anchor, out targetLocation);
throw new ArgumentException("Error during relocation: Can not relocate " + tileAtOriginalPosition.Location + " to its new position from anchor " + anchor.Location);
}
}
}
else if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.Vivado)
{
if (!IdentifierManager.Instance.IsMatch(anchor.Location, IdentifierManager.RegexTypes.CLB))
{
throw new ArgumentException("Error during relocation: Can only place on CLBs");
}
Tile interconnect = FPGATypes.GetInterconnectTile(anchor);
Tile clbKey = m_portsToBlock.Keys.FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile intKey = m_portsToBlock.Keys.FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.Interconnect));
if (clbKey != null)
{
Tuple <Tile, List <Port> > clbResult = new Tuple <Tile, List <Port> >(anchor, new List <Port>());
m_portsToBlock[clbKey].ForEach(s => clbResult.Item2.Add(new Port(s)));
yield return(clbResult);
}
if (intKey != null)
{
Tuple <Tile, List <Port> > intResult = new Tuple <Tile, List <Port> >(interconnect, new List <Port>());
m_portsToBlock[intKey].ForEach(s => intResult.Item2.Add(new Port(s)));
yield return(intResult);
}
}
}
protected override void DoCommandAction()
{
if (!RAMSelectionManager.Instance.HasMappings)
{
RAMSelectionManager.Instance.UpdateMapping();
}
List <Tile> expansion = new List <Tile>();
// get tiles to add
foreach (Tile t in TileSelectionManager.Instance.GetSelectedTiles())
{
if (IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(t);
if (intTile.LocationX == t.LocationX && intTile.LocationY == t.LocationY && IdentifierManager.Instance.IsMatch(intTile.Location, IdentifierManager.RegexTypes.Interconnect))
{
if (AddToSelection(intTile))
{
expansion.Add(intTile);
}
foreach (Tile clbTile in FPGATypes.GetCLTile(intTile))
{
if (AddToSelection(clbTile))
{
expansion.Add(clbTile);
}
}
}
}
if (IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.Interconnect))
{
foreach (Tile clbTile in FPGATypes.GetCLTile(t))
{
if (clbTile.LocationX == t.LocationX && clbTile.LocationY == t.LocationY && IdentifierManager.Instance.IsMatch(clbTile.Location, IdentifierManager.RegexTypes.CLB))
{
if (AddToSelection(clbTile))
{
expansion.Add(clbTile);
}
}
}
}
if (RAMSelectionManager.Instance.HasMapping(t))
{
foreach (Tile ramBlockMember in RAMSelectionManager.Instance.GetRamBlockMembers(t))
{
if (AddToSelection(ramBlockMember))
{
expansion.Add(ramBlockMember);
}
}
}
}
// expand selection
foreach (Tile t in expansion)
{
TileSelectionManager.Instance.AddToSelection(t.TileKey, false);
}
TileSelectionManager.Instance.SelectionChanged();
}
private void DrawNonRAMTile(Tile tile, Graphics graphicsObj, bool addIncrementForSelectedTiles, bool addIncrementForUserSelectedTiles)
{
int upperLeftX = 0;
int upperLeftY = 0;
int widthScale = 1;
int heightScale = 1;
if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(tile);
switch (FPGA.FPGA.Instance.Family)
{
case FPGATypes.FPGAFamily.Artix7:
case FPGATypes.FPGAFamily.Kintex7:
case FPGATypes.FPGAFamily.Virtex7:
case FPGATypes.FPGAFamily.Zynq:
{
if (FPGATypes.IsOrientedMatch(tile.Location, IdentifierManager.RegexTypes.CLB_left))
{
// CLBLL_L_X INT_L_X
upperLeftX = tile.TileKey.X * m_view.TileSize;
upperLeftY = tile.TileKey.Y * m_view.TileSize;
widthScale = 2;
}
else
{
upperLeftX = intTile.TileKey.X * m_view.TileSize;
upperLeftY = intTile.TileKey.Y * m_view.TileSize;
// double size of the rectangle
widthScale = 2;
}
break;
}
case FPGATypes.FPGAFamily.UltraScale:
{
widthScale = FPGATypes.GetCLTile(intTile).Count() + 1;
if (FPGATypes.IsOrientedMatch(tile.Location, IdentifierManager.RegexTypes.CLB_left))
{
// CLBLL_L_X INT_L_X
upperLeftX = tile.TileKey.X * m_view.TileSize;
upperLeftY = tile.TileKey.Y * m_view.TileSize;
}
else
{
upperLeftX = (intTile.TileKey.X - (widthScale == 2 ? 0 : 1)) * m_view.TileSize;
upperLeftY = intTile.TileKey.Y * m_view.TileSize;
// double size of the rectangle
}
break;
}
default:
{
upperLeftX = intTile.TileKey.X * m_view.TileSize;
upperLeftY = intTile.TileKey.Y * m_view.TileSize;
// double size of the rectangle
widthScale = 2;
break;
}
}
}
else if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.Interconnect))
{
// interconnect tiles for CLB have no tiles
return;
}
else
{
upperLeftX = tile.TileKey.X * m_view.TileSize;
upperLeftY = tile.TileKey.Y * m_view.TileSize;
}
m_rect.X = upperLeftX - 1;
m_rect.Y = upperLeftY - 1;
m_rect.Width = (widthScale * (m_view.TileSize - 1) + widthScale) - 2;
m_rect.Height = (heightScale * (m_view.TileSize - 1) + heightScale) - 2;
// default color maybde overwritten
m_sb.Color = m_view.GetColor(tile, addIncrementForSelectedTiles, addIncrementForUserSelectedTiles);
graphicsObj.FillRectangle(m_sb, m_rect);
}
private void DeriveBlockingData(LibraryElement libElement)
{
////////////////////////////
// find LOGICIN and LOGICOUT
foreach (XDLPort xdlPort in ((XDLContainer)libElement.Containter).Ports)
{
XDLInstance inst = (XDLInstance)libElement.Containter.GetInstanceByName(xdlPort.InstanceName);
Tile clb = FPGA.FPGA.Instance.GetTile(inst.Location);
Tile interconnectTile = FPGATypes.GetInterconnectTile(clb);
Slice slice = clb.GetSliceByName(inst.SliceName);
// true: in, false: out (no needed)
Dictionary <uint, bool> portMapping = new Dictionary <uint, bool>();
foreach (Port inPort in slice.PortMapping.GetPorts(FPGATypes.PortDirection.In))
{
portMapping.Add(inPort.NameKey, true);
}
// 1 store all ports we need to connect the switchmatrx with macro in ports
foreach (Tuple <Port, Port> intArc in interconnectTile.SwitchMatrix.GetAllArcs())
{
bool portFound = false;
// find the arc that is driven by the xdlPort && make sure that we get the correct slice
foreach (Location loc in Navigator.GetDestinations(interconnectTile, intArc.Item2).Where(l => l.Tile.Location.Equals(clb.Location)))
{
foreach (Port clbPort in clb.SwitchMatrix.GetDrivenPorts(loc.Pip).Where(drivenPort => portMapping.ContainsKey(drivenPort.NameKey) && drivenPort.Name.EndsWith(xdlPort.SlicePort)))
{
libElement.AddPortToBlock(interconnectTile, intArc.Item2);
portFound = true;
break;
}
if (portFound)
{
break;
}
}
}
// 2 store all ports we need to connect the macro out ports to the switch matrix (LOGICOUT\d+)
// // find the arc that is driven by the xdlPort && make sure that we get the correct slice
foreach (Tuple <Port, Port> arc in clb.SwitchMatrix.GetAllArcs().Where(a => slice.PortMapping.IsSliceOutPort(a.Item1) && a.Item1.Name.EndsWith(xdlPort.SlicePort)))
{
foreach (Location loc in Navigator.GetDestinations(clb, arc.Item2))
{
libElement.AddPortToBlock(loc.Tile, loc.Pip);
}
}
}
////////////////////////////
// extract begin pips to block
foreach (XDLNet net in libElement.Containter.Nets)
{
foreach (XDLPip pip in net.Pips)
{
libElement.AddPortToBlock(FPGA.FPGA.Instance.GetTile(pip.Location), new Port(pip.From));
libElement.AddPortToBlock(FPGA.FPGA.Instance.GetTile(pip.Location), new Port(pip.To));
}
}
// sideeffect, trigger calculation of slice number to reuse this macro on other devices
foreach (XDLInstance inst in libElement.Containter.Instances)
{
inst.DeriveTileKeyAndSliceNumber();
}
// CLB anchor
if (((XDLContainer)libElement.Containter).ExplicitAnchorFound)
{
if (((XDLContainer)libElement.Containter).HasInstanceByName(((XDLContainer)libElement.Containter).Anchor))
{
XDLInstance anchorInst = (XDLInstance)libElement.Containter.GetInstanceByName(((XDLContainer)libElement.Containter).Anchor);
libElement.ResourceShape.Anchor.AnchorLocationX = anchorInst.LocationX;
libElement.ResourceShape.Anchor.AnchorLocationY = anchorInst.LocationY;
libElement.ResourceShape.Anchor.AnchorSliceName = anchorInst.SliceName;
libElement.ResourceShape.Anchor.AnchorSliceNumber = anchorInst.SliceNumber;
libElement.ResourceShape.Anchor.AnchorTileLocation = anchorInst.Location;
}
else
{
Slice anchorSlice = FPGA.FPGA.Instance.GetSlice(((XDLContainer)libElement.Containter).Anchor);
libElement.ResourceShape.Anchor.AnchorLocationX = anchorSlice.ContainingTile.LocationX;
libElement.ResourceShape.Anchor.AnchorLocationY = anchorSlice.ContainingTile.LocationY;
libElement.ResourceShape.Anchor.AnchorSliceName = anchorSlice.SliceName;
libElement.ResourceShape.Anchor.AnchorSliceNumber = 0; // see CutOffFromDesign
libElement.ResourceShape.Anchor.AnchorTileLocation = anchorSlice.ContainingTile.Location;
}
}
else
{
// TODO der Slot muss ausgewaehlt sein!
SetResourceShapeInfo setCmd = new SetResourceShapeInfo();
setCmd.LibraryElementName = libElement.Name;
CommandExecuter.Instance.Execute(setCmd);
}
}
public AddBlockToSelection(int x1, int y1, int x2, int y2)
{
// run form min to max
int startX = Math.Min(x1, x2);
int endX = Math.Max(x1, x2);
int startY = Math.Min(y1, y2);
int endY = Math.Max(y1, y2);
int maxX = int.MinValue;
int minX = int.MaxValue;
int maxY = int.MinValue;
int minY = int.MaxValue;
Tile ul = null;
Tile lr = null;
for (int x = startX; x <= endX; x++)
{
for (int y = startY; y <= endY; y++)
{
// click done out of FPGA range
if (!FPGA.FPGA.Instance.Contains(x, y))
{
continue;
}
Tile t = FPGA.FPGA.Instance.GetTile(x, y);
UpdateUpperLeftAndLowerRightCorner(ref maxX, ref minX, ref maxY, ref minY, ref ul, ref lr, t);
}
}
// clicked in BRAM/DSP block?
if ((ul == null || lr == null) && FPGA.FPGA.Instance.Contains(startX, endY))
{
Tile t = FPGA.FPGA.Instance.GetTile(startX, endY);
if (RAMSelectionManager.Instance.HasMapping(t))
{
foreach (Tile member in RAMSelectionManager.Instance.GetRamBlockMembers(t))
{
UpdateUpperLeftAndLowerRightCorner(ref maxX, ref minX, ref maxY, ref minY, ref ul, ref lr, member);
}
}
}
if (ul == null || lr == null)
{
throw new ArgumentException("Could not derive upper left and lower right anchor");
}
// go from CLB to INT
if (IdentifierManager.Instance.IsMatch(ul.Location, IdentifierManager.RegexTypes.CLB))
{
ul = FPGATypes.GetInterconnectTile(ul);
}
if (IdentifierManager.Instance.IsMatch(lr.Location, IdentifierManager.RegexTypes.CLB))
{
lr = FPGATypes.GetInterconnectTile(lr);
}
UpperLeftTile = ul.Location;
LowerRightTile = lr.Location;
}
protected override void DoCommandAction()
{
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
Dictionary <Port, List <Tuple <Port, Port> > > result = new Dictionary <Port, List <Tuple <Port, Port> > >();
foreach (string portName in EndPorts)
{
Port endPort = new Port(portName);
result.Add(endPort, new List <Tuple <Port, Port> >());
foreach (Port imux in interconnect.SwitchMatrix.GetDrivenPorts(endPort).Where(p => Regex.IsMatch(p.Name, IMUX)))
{
Location l = Navigator.GetDestinations(interconnect, imux).FirstOrDefault();
foreach (Port lutInPort in clb.SwitchMatrix.GetDrivenPorts(l.Pip).Where(p => Regex.IsMatch(p.Name, LUTInPortFilter)))
{
result[endPort].Add(new Tuple <Port, Port>(imux, lutInPort));
}
}
}
// valid
bool noMatches = result.Values.Any(l => l.Count == 0);
if (noMatches)
{
OutputManager.WriteWarning("Could not enter LUT via all ports -> exit command");
return;
}
// look for unique paths
foreach (KeyValuePair <Port, List <Tuple <Port, Port> > > portTupleList in result)
{
IEnumerable <KeyValuePair <Port, List <Tuple <Port, Port> > > > others = result.Where(t => !t.Key.Equals(portTupleList.Key));
Port takenInput = null;
foreach (Tuple <Port, Port> tuple in portTupleList.Value)
{
// t => t.Value.Count == 0 becomes true if the already took some ports
if (others.All(t => t.Value.Count == 0 || t.Value.Any(p => !p.Equals(tuple.Item2))))
{
// found mapping
OutputManager.WriteOutput(portTupleList.Key.Name + " -> " + tuple.Item1.Name + " -> " + tuple.Item2.Name);
takenInput = tuple.Item2;
break;
}
else
{
// try next one
}
}
if (takenInput == null)
{
OutputManager.WriteWarning("Did not find an unique LUT inpt for " + portTupleList.Key.Name + " -> exit command");
return;
}
foreach (KeyValuePair <Port, List <Tuple <Port, Port> > > t in result)
{
t.Value.RemoveAll(p => p.Equals(takenInput));
}
// all other tuples must have a LUT in port different from the current one
//bool unique = result.Where(other => tuple.Key.Equals(other.Key)).All(t => t.Value.FirstOrDefault(p => p.NameKey != tuple.Value[0]));
}
}
