public ModelingSystemCore(VHDL.libraryunit.Architecture architecture, VHDL.LibraryDeclarativeRegion library, VHDL.RootDeclarativeRegion rootDeclarationRegion) { ExpressionEvaluator.DefaultEvaluator = new ExpressionEvaluator(this); this.architecture = architecture; this.library = library; this.rootDeclarationRegion = rootDeclarationRegion; functionAnalyser = new FunctionAnalyser(architecture.Scope); currentScope = new List <IValueProvider>(); signalScope = new List <Signal>(); now = new TIME_VALUE(0); FormDefaultResultScope(); }
public ModelingSystemCore(VHDL.libraryunit.Architecture architecture, VHDL.LibraryDeclarativeRegion library, VHDL.RootDeclarativeRegion rootDeclarationRegion, SimulationScope scope) { ExpressionEvaluator.DefaultEvaluator = new ExpressionEvaluator(this); this.architecture = architecture; this.library = library; this.rootDeclarationRegion = rootDeclarationRegion; functionAnalyser = new FunctionAnalyser(architecture.Scope); currentScope = new List <IValueProvider>(); signalScope = new List <Signal>(); now = new TIME_VALUE(0); result_scope = scope; foreach (var s in scope.Variables) { if (s is Signal) { signalScope.Add(s as Signal); currentScope.Add(s as Signal); } } }