public static void RunTest()
{
DesignContext.Reset();
TestDesign1 td1 = new TestDesign1(3, 4);
FixedPointSettings.GlobalOverflowMode = EOverflowMode.Wrap;
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(20 * TestDesign1.ClockPeriod);
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_TestDesign1", "TestDesign1");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);;
project.Save();
DesignContext.Reset();
}
static void Main(string[] args)
{
Console.WriteLine("SystemSharp test cases");
Console.WriteLine();
try
{
Console.WriteLine("Part 1: Basic data structures");
Console.WriteLine(" testing SystemSharp.Collections.EmilStefanov.DisjointSets");
SystemSharp.Collections.EmilStefanov.Test.DisjointSetsTester.RunTests();
Console.WriteLine(" testing fixed point math");
TestFixPoint.RunTest();
Console.WriteLine("Part 2: Design analysis and synthesis");
TestDesign1.RunTest();
TestRegPipe.RunTest();
TestAddMul0.RunTest();
TestAddMul1.RunTest();
TestAddMul2.RunTest();
Mod2TestDesign.Run();
TestConcatTestbench.Run();
Console.WriteLine("Part 3: Compiler");
CompilerTest.Testbench.RunTest();
Console.WriteLine("Part 4: Component tests");
ALUTestDesign.Run();
Mod2TestDesign.Run();
Test_SinCosLUT_Testbench.RunTest();
Console.WriteLine("Part 5: HLS");
TestHLS_PortAccess_Testbench.RunTest();
TestHLS_ALU_Testbench.RunTest();
TestHLS_FPU_Testbench.RunTest();
TestHLS_Cordic_Testbench.RunTest();
TestHLS_CordicSqrt_Testbench.RunTest();
TestHLS_CFlow_Testbench.RunTest();
TestHLS_CFlow2_Testbench.RunTest();
TestHLS_VanDerPol_Testbench.RunTest();
TestHLSTestbench1.RunTest();
TestHLS_SFixDiv.RunTest();
TestHLS_SinCosLUT_Testbench.RunTest();
Console.WriteLine("Part 6: File writing");
FileWriterTestbench.RunTest();
Console.WriteLine();
Console.WriteLine("Test passed");
}
catch (Exception e)
{
Console.WriteLine("Test failed: " + e.Message);
}
}
public static void RunTest()
{
DesignContext.Reset();
TestDesign1 td1 = new TestDesign1(3, 4);
FixedPointSettings.GlobalOverflowMode = EOverflowMode.Wrap;
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(20 * TestDesign1.ClockPeriod);
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_TestDesign1", "TestDesign1");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen); ;
project.Save();
DesignContext.Reset();
}