public static void RunTest()
{
DesignContext.Reset();
FixedPointSettings.GlobalArithSizingMode = EArithSizingMode.VHDLCompliant;
var a = SFix.FromDouble(1.0, 8, 10);
var b = SFix.FromDouble(2.0, 8, 10);
var c = SFix.FromDouble(3.0, 8, 10);
var d = SFix.FromDouble(4.0, 8, 10);
TestAddMul0 dut = new TestAddMul0()
{
A = new Signal<SFix>() { InitialValue = a },
B = new Signal<SFix>() { InitialValue = b },
C = new Signal<SFix>() { InitialValue = c },
D = new Signal<SFix>() { InitialValue = d },
R = new Signal<SFix>() { InitialValue = a * b + c * d }
};
DesignContext.Instance.Elaborate();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX240T_FF1156 fpga = new XC6VLX240T_FF1156()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = dut
};
fpga.Synthesize(@".\hdl_out_TestAddMul0", "TestAddMul0");
}
public static void GenerateFloatingPointCores()
{
var ise = ISEDetector.DetectMostRecentISEInstallation();
DesignContext.Reset();
var fpu = new FPUWrapper(ise.VersionTag);
DesignContext.Instance.Elaborate();
var fpga = new XC6VLX240T_FF1156();
fpga.SpeedGrade = ESpeedGrade._2;
fpga.TopLevelComponent = fpu;
var proj = fpga.Synthesize("c:\\temp\\fputest", "fpu", null,
EFlowStep.HDLGen | EFlowStep.IPCores);
var flow = proj.ConfigureFlow(fpu);
flow.TRCE.ReportUnconstrainedPaths = true;
flow.Start(
EFlowStep.XST |
EFlowStep.NGDBuild |
EFlowStep.Map |
EFlowStep.PAR |
EFlowStep.TRCE);
proj.AwaitRunningToolsToFinish();
PerformanceRecord designRec;
ResourceRecord deviceRec;
flow.ParseResourceRecords(out designRec, out deviceRec);
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_VanDerPol_Testbench tb = new TestHLS_VanDerPol_Testbench();
DesignContext.Instance.Elaborate();
//DesignContext.Instance.Simulate(new Time(4.0, ETimeUnit.us));
//DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX240T_FF1156 fpga = new XC6VLX240T_FF1156()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = tb.DUT
};
fpga.Testbenches.Add(tb);
fpga.Pins["J9"].Map(tb.DUT.Clk);
fpga.Synthesize(@".\hdl_out_TestHLS_VanDerPol", "TestHLS_VanDerPol");
}
public static void RunTest()
{
DesignContext.Reset();
FixedPointSettings.GlobalArithSizingMode = EArithSizingMode.InSizeIsOutSize;
var design = new TestHLS_SFixDiv(8, 32);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX240T_FF1156 fpga = new XC6VLX240T_FF1156()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = design
};
fpga.Testbenches.Add(design);
fpga.Synthesize(@".\hdl_out_TestHLS_SFixDiv", "TestHLS_SFixDiv");
}