private static bool J(uint u, RiscVDisassembler d)
{
var offset = Bitfield.ReadSignedFields(j_bitfields, u) << 1;
d.state.ops.Add(AddressOperand.Create(d.addrInstr + offset));
return(true);
}
// signed offset used in loads
private static bool Ls(uint wInstr, RiscVDisassembler dasm)
{
var op = dasm.GetImmediate(wInstr, 20, 's');
dasm.state.ops.Add(op);
return(true);
}
private static bool Z(uint wInstr, RiscVDisassembler dasm)
{
var op = dasm.GetShiftAmount(wInstr, 6);
dasm.state.ops.Add(op);
return(true);
}
private static bool B(uint wInstr, RiscVDisassembler dasm)
{
var op = dasm.GetBranchTarget(wInstr);
dasm.state.ops.Add(op);
return(true);
}
private static bool r1(uint wInstr, RiscVDisassembler dasm)
{
var op = dasm.GetRegister(wInstr, 15);
dasm.state.ops.Add(op);
return(true);
}
private static bool Iu(uint wInstr, RiscVDisassembler dasm)
{
uint u = wInstr >> 12;
var op = ImmediateOperand.Word32(u);
dasm.state.ops.Add(op);
return(true);
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint wInstr)
{
var slot = (int)((wInstr >> shift) & mask);
if (!subcodes.TryGetValue(slot, out Decoder decoder))
{
return(dasm.MakeInvalid());
}
return(decoder.Decode(dasm, wInstr));
}
private static bool Csr20(uint uInstr, RiscVDisassembler dasm)
{
var iCsr = bf20_12.Read(uInstr);
if (!dasm.arch.Csrs.TryGetValue(iCsr, out var csr))
{
return(false); //$REVIEW: should raise a warning? This could be model-specific.
}
dasm.state.ops.Add(new RegisterOperand(csr));
return(true);
}
public override RiscVInstruction Decode(uint hInstr, RiscVDisassembler dasm)
{
if (!dasm.rdr.TryReadUInt16(out ushort hiword))
{
return(dasm.CreateInvalidInstruction());
}
uint wInstr = (uint)hiword << 16;
wInstr |= hInstr;
return(subDecoders.Decode(wInstr, dasm));
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint hInstr)
{
ushort hiword;
if (!dasm.rdr.TryReadUInt16(out hiword))
{
return new RiscVInstruction { opcode = Opcode.invalid, Address = dasm.addrInstr };
}
uint wInstr = (uint)hiword << 16;
wInstr |= hInstr;
var slot = (wInstr >> 2) & 0x1F;
return wideOpRecs[slot].Decode(dasm, wInstr);
}
public override RiscVInstruction Decode(uint wInstr, RiscVDisassembler dasm)
{
switch (dasm.arch.WordWidth.Size)
{
case 4: return(rv32.Decode(wInstr, dasm));
case 8: return(rv64.Decode(wInstr, dasm));
case 16: return(rv128.Decode(wInstr, dasm));
}
throw new NotSupportedException($"{dasm.arch.WordWidth.Size}-bit Risc-V instructions not supported.");
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint hInstr)
{
var value = mask.Read(hInstr);
if (predicate(value))
{
return(trueDecoder.Decode(dasm, hInstr));
}
else
{
return(falseDecoder.Decode(dasm, hInstr));
}
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint hInstr)
{
if (!dasm.rdr.TryReadUInt16(out ushort hiword))
{
return(dasm.MakeInvalid());
}
uint wInstr = (uint)hiword << 16;
wInstr |= hInstr;
var slot = (wInstr >> 2) & 0x1F;
return(w32decoders[slot].Decode(dasm, wInstr));
}
public override RiscVInstruction Decode(uint wInstr, RiscVDisassembler dasm)
{
dasm.state.instr.InstructionClass = InstrClass.Linear;
dasm.state.instr.Mnemonic = opcode;
dasm.state.ops.Clear();
foreach (var m in mutators)
{
if (!m(wInstr, dasm))
{
return(dasm.CreateInvalidInstruction());
}
}
return(dasm.MakeInstruction());
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint wInstr)
{
var slot = (int)((wInstr >> shift) & mask);
OpRec oprec;
if (!subcodes.TryGetValue(slot, out oprec))
{
return new RiscVInstruction
{
Address = dasm.addrInstr,
opcode = Opcode.invalid
};
}
return oprec.Decode(dasm, wInstr);
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint wInstr)
{
dasm.state.instr.iclass = InstrClass.Linear;
dasm.state.instr.opcode = opcode;
dasm.state.ops.Clear();
foreach (var m in mutators)
{
if (!m(wInstr, dasm))
{
return(dasm.MakeInvalid());
}
}
return(dasm.MakeInstruction());
}
public override RiscVInstruction Decode(uint wInstr, RiscVDisassembler dasm)
{
var decoder = decoders[bit(wInstr, 30) ? 1 : 0];
return(decoder.Decode(wInstr, dasm));
}
public override RiscVInstruction Decode(uint hInstr, RiscVDisassembler dasm)
{
return(dasm.NotYetImplemented(hInstr, message));
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint wInstr)
{
return(dasm.DecodeCompressedOperands(opcode, fmt, wInstr));
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint wInstr)
{
var opcode = rl_ra[bit(wInstr, 30) ? 1 : 0];
return(dasm.DecodeWideOperands(opcode, InstrClass.Linear, fmt, wInstr));
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint wInstr)
{
var slot = (wInstr >> shift) & mask;
return(subcodes[slot].Decode(dasm, wInstr));
}
public abstract RiscVInstruction Decode(RiscVDisassembler dasm, uint hInstr);
/// <summary>
/// Acquire/release bits
/// </summary>
private static bool aq_rl(uint uInstr, RiscVDisassembler dasm)
{
dasm.state.instr.Acquire = Bits.IsBitSet(uInstr, 26);
dasm.state.instr.Release = Bits.IsBitSet(uInstr, 25);
return(true);
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint wInstr)
{
return dasm.DecodeWideOperands(opcode, fmt, wInstr);
}
public override RiscVInstruction Decode(RiscVDisassembler dasm, uint wInstr)
{
return(dasm.DecodeWideOperands(opcode, InstrClass.Linear, fmt, wInstr));
}
