void EmitUnitTest(BlackfinInstruction instr)
{
if (opcode_seen.Contains(instr.Mnemonic))
{
return;
}
opcode_seen.Add(instr.Mnemonic);
var r2 = rdr.Clone();
r2.Offset -= instr.Length;
Console.WriteLine(" [Test]");
Console.WriteLine(" public void BlackfinRw_{0}()", instr.Mnemonic);
Console.WriteLine(" {");
if (instr.Length > 2)
{
var wInstr = r2.ReadBeUInt32();
Console.WriteLine($" RewriteCode(\"{wInstr:X8}\"); // {instr}");
}
else
{
var wInstr = r2.ReadBeUInt16();
Console.WriteLine($" RewriteCode(\"{wInstr:X4}\"); // {instr}");
}
Console.WriteLine(" AssertCode(");
Console.WriteLine($" \"0|L--|00100000({instr.Length}): 1 instructions\",");
Console.WriteLine($" \"1|L--|@@@\");");
Console.WriteLine(" }");
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
this.instr = dasm.Current;
var rtls = new List <RtlInstruction>();
this.m = new RtlEmitter(rtls);
this.iclass = instr.InstructionClass;
switch (instr.Mnemonic)
{
default:
EmitUnitTest(instr);
iclass = InstrClass.Invalid;
goto case Mnemonic.invalid;
case Mnemonic.invalid:
this.iclass = InstrClass.Invalid;
m.Invalid();
break;
}
yield return(new RtlInstructionCluster(instr.Address, instr.Length, rtls.ToArray())
{
Class = iclass
});
}
}
public BlackfinRewriter(BlackfinArchitecture arch, EndianImageReader rdr, ProcessorState state, IStorageBinder binder, IRewriterHost host)
{
this.arch = arch;
this.rdr = rdr;
this.state = state;
this.binder = binder;
this.host = host;
this.dasm = new BlackfinDisassembler(arch, rdr).GetEnumerator();
this.instr = null !;
this.m = null !;
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
this.instr = dasm.Current;
var rtls = new List <RtlInstruction>();
this.m = new RtlEmitter(rtls);
this.iclass = instr.InstructionClass;
switch (instr.Mnemonic)
{
default:
EmitUnitTest(instr);
iclass = InstrClass.Invalid;
goto case Mnemonic.invalid;
case Mnemonic.invalid:
this.iclass = InstrClass.Invalid;
m.Invalid();
break;
case Mnemonic.CLI: RewriteCli(); break;
case Mnemonic.mov: RewriteMov(); break;
case Mnemonic.mov_x: RewriteMovx(); break;
case Mnemonic.mov_xb: RewriteMovxb(); break;
case Mnemonic.mov_zb: RewriteMovzb(); break;
case Mnemonic.mul: RewriteMul(); break;
case Mnemonic.JUMP_L: RewriteJump(); break;
case Mnemonic.RTN: RewriteRtn(); break;
case Mnemonic.RTS: RewriteRts(); break;
case Mnemonic.sub3: RewriteBinop(m.ISub); break;
case Mnemonic.xor3: RewriteBinop(m.Xor); break;
}
yield return(new RtlInstructionCluster(instr.Address, instr.Length, rtls.ToArray())
{
Class = iclass
});
}
}
private void EmitUnitTest(BlackfinInstruction instr)
{
var testGenSvc = arch.Services.GetService <ITestGenerationService>();
testGenSvc?.ReportMissingRewriter("BlackfinRw", instr, instr.Mnemonic.ToString(), rdr, "");
}