public void Initialize()
{
ulong clockticks = GetUncorePerfEvtSelRegisterValue(0, 0, false, false, false, true, false, 0);
ulong llcLookup = GetUncorePerfEvtSelRegisterValue(0x34, 0xF, false, false, false, true, false, 0);
// event 0x1B = AD ring
ulong adRingUp = GetUncorePerfEvtSelRegisterValue(0x1B, RING_UP_EVEN | RING_UP_ODD, false, false, false, true, false, 0);
ulong adRingDn = GetUncorePerfEvtSelRegisterValue(0x1B, RING_DN_EVEN | RING_DN_ODD, false, false, false, true, false, 0);
ulong filter = GetUncoreFilterRegisterValue(0, 0x1, LLC_LOOKUP_I, 0);
cpu.SetupMonitoringSession(llcLookup, clockticks, adRingUp, adRingDn, filter);
}
public void Initialize()
{
ulong clockticks = GetUncorePerfEvtSelRegisterValue(0, 0, false, false, false, true, false, 0);
// Ring response bounces, include AK/BL/IV
ulong bounces = GetUncorePerfEvtSelRegisterValue(0x5, 0b111, false, false, false, true, false, 0);;
// event 0x1C = AK ring
ulong akRingUp = GetUncorePerfEvtSelRegisterValue(0x1C, RING_UP_EVEN | RING_UP_ODD, false, false, false, true, false, 0);
ulong akRingDn = GetUncorePerfEvtSelRegisterValue(0x1C, RING_DN_EVEN | RING_DN_ODD, false, false, false, true, false, 0);
ulong filter = GetUncoreFilterRegisterValue(0, 0x1, 0x1F, 0); // doesn't matter
cpu.SetupMonitoringSession(bounces, clockticks, akRingUp, akRingDn, filter);
}
public void Initialize()
{
ulong clockticks = GetUncorePerfEvtSelRegisterValue(0, 0, false, false, false, true, false, 0);
// LLC victim in M (modified) state = 64B writeback. ctr0 or ctr1
ulong llcWbVictims = GetUncorePerfEvtSelRegisterValue(0x37, 1, false, false, false, true, false, 0);;
// event 0x1E = IV ring
ulong ivRingOdd = GetUncorePerfEvtSelRegisterValue(0x1E, RING_UP_ODD | RING_DN_ODD, false, false, false, true, false, 0);
ulong ivRingEven = GetUncorePerfEvtSelRegisterValue(0x1E, RING_UP_EVEN | RING_DN_ODD, false, false, false, true, false, 0);
ulong filter = GetUncoreFilterRegisterValue(0, 0x1, LLC_LOOKUP_I, 0); // doesn't matter
cpu.SetupMonitoringSession(llcWbVictims, clockticks, ivRingOdd, ivRingEven, filter);
}
public void Initialize()
{
// umask 0b1 = filter (mandatory), 0b10 = data read, 0b100 = write, 0b1000 = remote snoop. LLC lookup must go in ctr0 or ctr1
ulong clockticks = GetUncorePerfEvtSelRegisterValue(0, 0, false, false, false, true, false, 0);
ulong llcLookup = GetUncorePerfEvtSelRegisterValue(0x34, 0xF, false, false, false, true, false, 0);
// 0x1D = BL ring (block/data ring) used cycles, 0b1 = up direction even polarity. 0b10 = up direction odd polarity. must go in ctr2 or ctr3
ulong blRingUp = GetUncorePerfEvtSelRegisterValue(0x1D, RING_UP_EVEN | RING_UP_ODD, false, false, false, true, false, 0);
// 0b100 = down direction even polarity, 0b1000 = down direction odd polarity
ulong blRingDn = GetUncorePerfEvtSelRegisterValue(0x1D, RING_DN_EVEN | RING_DN_ODD, false, false, false, true, false, 0);
ulong filter = GetUncoreFilterRegisterValue(0, 0x1, LLC_LOOKUP_E | LLC_LOOKUP_F | LLC_LOOKUP_M | LLC_LOOKUP_S, 0);
cpu.SetupMonitoringSession(clockticks, llcLookup, blRingUp, blRingDn, filter);
}
public void Initialize()
{
// no counter restrictions for clockticks
ulong clockticks = GetUncorePerfEvtSelRegisterValue(0, 0, false, false, false, true, false, 0);
// 0x11 = ingress occupancy. umask 1 = ingress request queue (core requests). must be in ctr0
ulong rxrOccupancy = GetUncorePerfEvtSelRegisterValue(0x11, 1, false, false, false, true, false, 0);
// 0x13 = ingress allocations. umask = 1 = irq (Ingress Request Queue = core requests). must be in ctr0 or ctr1
ulong rxrInserts = GetUncorePerfEvtSelRegisterValue(0x13, 1, false, false, false, true, false, 0);
// 0x1F = counter 0 occupancy. cmask = 1 to count cycles when ingress queue isn't empty
ulong rxrEntryPresent = GetUncorePerfEvtSelRegisterValue(0x1F, 0xFF, false, false, false, true, false, 1);
ulong filter = GetUncoreFilterRegisterValue(0, 0x1, LLC_LOOKUP_E | LLC_LOOKUP_F | LLC_LOOKUP_M | LLC_LOOKUP_S, 0);
cpu.SetupMonitoringSession(rxrOccupancy, rxrInserts, clockticks, rxrEntryPresent, filter);
}
public void Initialize()
{
// no counter restrictions for clockticks
ulong clockticks = GetUncorePerfEvtSelRegisterValue(0, 0, false, false, false, true, false, 0);
// 0x36 = tor occupancy, 0b1000 = all valid ToR entries
ulong torOccupancy = GetUncorePerfEvtSelRegisterValue(0x36, 0b1000, false, false, false, true, false, 0);
// 0x35 = tor inserts. 0b1000 not documented but other umasks are the same so let's try
ulong torInserts = GetUncorePerfEvtSelRegisterValue(0x35, 0b1000, false, false, false, true, false, 0);
// 0x1F = counter 0 occupancy. cmask = 1 to count cycles when there are valid entries in the ToR
ulong missPresent = GetUncorePerfEvtSelRegisterValue(0x1D, 0xFF, false, false, false, true, false, 1);
// filter not used, low bit of umask not set for ToR events
ulong filter = GetUncoreFilterRegisterValue(0, 0x1, LLC_LOOKUP_E | LLC_LOOKUP_F | LLC_LOOKUP_M | LLC_LOOKUP_S, 0x182);
cpu.SetupMonitoringSession(torOccupancy, torInserts, clockticks, missPresent, filter);
}
public void Initialize()
{
// no counter restrictions for clockticks
ulong clockticks = GetUncorePerfEvtSelRegisterValue(0, 0, false, false, false, true, false, 0);
// 0x36 = tor occupancy, 0b11 = miss transactions, and use opcode filter
ulong torOccupancy = GetUncorePerfEvtSelRegisterValue(0x36, 0b11, false, false, false, true, false, 0);
// 0x35 = tor inserts, 0b11 = miss transactions, use opcode filter
ulong torInserts = GetUncorePerfEvtSelRegisterValue(0x35, 0b11, false, false, false, true, false, 0);
// 0x1F = counter 0 occupancy. cmask = 1 to count cycles when data read is present
ulong missPresent = GetUncorePerfEvtSelRegisterValue(0x1F, 0xFF, false, false, false, true, false, 1);
// opcode 0x182 = demand data read, but opcode field is only 8 bits wide. wtf.
// try with just lower 8 bits
ulong filter = GetUncoreFilterRegisterValue(0, 0x1, LLC_LOOKUP_E | LLC_LOOKUP_F | LLC_LOOKUP_M | LLC_LOOKUP_S, 0x182);
cpu.SetupMonitoringSession(torOccupancy, torInserts, clockticks, missPresent, filter);
}