public void run() { UInt64 execution = UInt64.MaxValue; if (Config.sim_type == SIM_TYPE.cycle) { execution = Config.sim_cycle; } for (UInt64 i = 0; i < execution; i++) { trace.Step(); ins_p.Step(); foreach (var mem in MemorySelector.MemoryInfo) { if (GlobalTimer.ifMemoryStep(0)) { mem.Item3.Step(); } } Mctrl.Step(); PIMMctrl.Step(); for (int j = 0; j < Config.N; j++) { if (GlobalTimer.ifProcStep(j)) { proc[j].Step(); } } if (GlobalTimer.ifPIMUnitStep(0)) { pim.Step(); } if (Config.sim_type == SIM_TYPE.file) { bool done = true; proc.ForEach(x => done = done && x.done()); if (Config.use_pim) { pim.unit.ForEach(x => done = done && x.done()); } MemorySelector.MemoryInfo.ForEach(x => done = done && x.Item3.done()); if (done & ins_p.done() & Mctrl.done() & PIMMctrl.done()) { return; } } GlobalTimer.Step(); } }
public PIMSimulator(string[] args) { initAllconfigs(args); trace = new TraceFetcher(); ins_p = new InsPartition(); pg = new PageConverter(); if (Config.shared_cache) { shared_cache = new Shared_Cache(); } proc = new List <Proc>(); for (int i = 0; i < Config.N; i++) { Proc to_add = new Proc(ref ins_p, i); if (Config.shared_cache) { to_add.attach_shared_cache(ref shared_cache); } to_add.attach_tlb(ref pg); proc.Add(to_add); } int count = 0; foreach (var item in Config.memory) { if (item.Key.Equals("HMC")) { var tp = new HMCMem(count++) as MemObject; MemorySelector.add(item.Value, ref tp); } else { if (item.Key.Equals("DRAM") || item.Key.Equals("PCM")) { var tp = new DDRMem(count++) as MemObject; MemorySelector.add(item.Value, ref tp); } else { //error DEBUG.Error("Unknown Memory Type."); Environment.Exit(3); } } } Mctrl.init_queue(); PIMMctrl.init_queue(); pim = new PIM.PIM(ref ins_p); Coherence.init(); Coherence.linkproc(proc); GlobalTimer.InitClock(); BuildTopology(); }