public override void tick() { cycles++; //memory controllers for (int n = 0; n < Config.mem2.mctrl_num; n++) { for (int i = 0; i < Config.mem2.channel_max; i++) { mctrls2[n][i].tick(); } } while (reqs.Count > 0 && cycles - reqs.Peek().ts_arrival >= latency) { //********************************************************************************************************************************************* //yang Req req_temp = reqs.Peek(); Dbg.Assert(req_temp != null); if (mctrls2[Sim.get_mctrl(req_temp.pid)][req_temp.addr.cid].is_q_full(req_temp.pid, req_temp.type, req_temp.addr.rid, req_temp.addr.bid)) { break; } //********************************************************************************************************************************************* Req req = reqs.Dequeue(); Dbg.Assert(req != null); // req.ts_departure = cycles; // Dbg.Assert(req.ts_departure - req.ts_arrival > 0); if (req.type == ReqType.RD) { ////traverse crossbar //Sim.xbar.enqueue(req); //insert into mctrl insert_mctrl(req); } else { switch (Config.proc.cache_write_policy) { case "WriteThrough": // throw new System.Exception("Cache: Trying to service a write in a write-through cache."); break; case "WriteBack": //set_dirty(req); //Callback cb = req.callback; //Dbg.Assert(cb != null); //cb(req); insert_mctrl(req); break; } } } while (wbs.Count > 0) { Req wb_req = wbs.Peek(); Dbg.Assert(wb_req != null); MemAddr addr = wb_req.addr; /* if (mctrls2[Sim.get_mctrl(wb_req.pid)][addr.cid].is_q_full(wb_req.pid, wb_req.type, addr.rid, addr.bid)) * break; * * wbs.Dequeue(); * mctrls2[Sim.get_mctrl(wb_req.pid)][addr.cid].enqueue_req(wb_req);*/ //yang: if (Sim.mctrls[Sim.get_mctrl(wb_req.pid)][addr.cid].is_q_full(wb_req.pid, wb_req.type, addr.rid, addr.bid)) { break; } wbs.Dequeue(); Sim.mctrls[Sim.get_mctrl(wb_req.pid)][addr.cid].enqueue_req(wb_req); Stat.procs[wb_req.pid].cache_wb_req.Collect(); } if (Config.proc.cache_insertion_policy == "All") { Migration.tick(); } }