private void issue_req(Req req)
{
//remove request from waiting queue
List <Req> q = get_q(req);
Dbg.Assert(q.Contains(req));
q.Remove(req);
req.queueing_latency = (int)(cycles - req.ts_arrival);
total_queueing_latency[req.pid] += (ulong)req.queueing_latency;
if (Sim.highest_rank_proc == req.pid)
{
Sim.procs[req.pid].queueing_latency += (ulong)req.queueing_latency;
}
Stat.mctrls[cid].queueing_latency_per_proc[req.pid].Collect(req.queueing_latency);
//add to inflight queue
MemAddr addr = req.addr;
List <Req> inflight_q = inflightqs[addr.rid, addr.bid];
Dbg.Assert(inflight_q.Count < inflight_q.Capacity);
inflight_q.Add(req);
//add to command queue
List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid];
Dbg.Assert(cmd_q.Count == 0);
List <Cmd> new_cmd_q = decode_req(req);
Dbg.Assert(new_cmd_q.Count > 0);
cmd_q.AddRange(new_cmd_q);
Cmd cmd = cmd_q[0];
//meta_mctrl
meta_mctrl.issue_req(req);
req.ts_issue = cycles;
//stats
BankStat bstat = Stat.banks[addr.cid, addr.rid, addr.bid];
bstat.access.Collect();
if (cmd.type == Cmd.TypeEnum.PRECHARGE || cmd.type == Cmd.TypeEnum.ACTIVATE)
{
//bank stat
bstat.row_miss.Collect();
bstat.row_miss_perproc[req.pid].Collect();
//proc stat
if (cmd.req.type == ReqType.RD)
{
Stat.procs[req.pid].row_hit_rate_read.Collect(0);
Stat.procs[req.pid].row_miss_read.Collect();
}
else
{
Stat.procs[req.pid].row_hit_rate_write.Collect(0);
Stat.procs[req.pid].row_miss_write.Collect();
}
}
else
{
//bank stat
bstat.row_hit.Collect();
bstat.row_hit_perproc[req.pid].Collect();
//proc stat
if (cmd.req.type == ReqType.RD)
{
Stat.procs[req.pid].row_hit_rate_read.Collect(1);
Stat.procs[req.pid].row_hit_read.Collect();
}
else
{
Stat.procs[req.pid].row_hit_rate_write.Collect(1);
Stat.procs[req.pid].row_hit_write.Collect();
}
}
//issue command
issue_cmd(cmd);
}
private void issue_req(Req req)
{
//remove request from waiting queue
List <Req> q = get_q(req);
Dbg.Assert(q.Contains(req));
q.Remove(req);
//add to inflight queue
MemAddr addr = req.addr;
List <Req> inflight_q = inflightqs[addr.rid, addr.bid];
Dbg.Assert(inflight_q.Count < inflight_q.Capacity);
inflight_q.Add(req);
// if (inflight_q.Count != 1)
// Console.WriteLine("{0}",inflight_q.Count);
//add to command queue
List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid];
Dbg.Assert(cmd_q.Count == 0);
List <Cmd> new_cmd_q = decode_req(req);
Dbg.Assert(new_cmd_q.Count > 0);
cmd_q.AddRange(new_cmd_q);
Cmd cmd = cmd_q[0];
Dbg.Assert(cmd == new_cmd_q[0]);
//meta_mctrl
meta_mctrl.issue_req(req);
Dbg.Assert(cmd.req.addr.rowid == req.addr.rowid);
//stats
BankStat bstat = Stat.banks[addr.cid, addr.rid, addr.bid];
bstat.access.Collect();
if (cmd.type == Cmd.TypeEnum.PRECHARGE || cmd.type == Cmd.TypeEnum.ACTIVATE)
{
//bank stat
bstat.row_miss.Collect();
bstat.row_miss_perproc[req.pid].Collect();
//proc stat
if (cmd.req.type == ReqType.RD)
{
Stat.procs[req.pid].row_hit_rate_read.Collect(0);
Stat.procs[req.pid].row_miss_read.Collect();
}
else
{
Stat.procs[req.pid].row_hit_rate_write.Collect(0);
Stat.procs[req.pid].row_miss_write.Collect();
}
req.hit = 2;
// Power Measurement:
Sim.NVM_power_statistics(req.pid, req.migrated_request, req.type, false);
//
if (Config.proc.cache_insertion_policy == "PFA")
{
// if ((!req.migrated_request) && (req.type == ReqType.RD))
Measurement.NVMMissSetRowBufferChange(req);
}
}
else
{
//bank stat
bstat.row_hit.Collect();
bstat.row_hit_perproc[req.pid].Collect();
//proc stat
if (cmd.req.type == ReqType.RD)
{
Stat.procs[req.pid].row_hit_rate_read.Collect(1);
Stat.procs[req.pid].row_hit_read.Collect();
}
else
{
Stat.procs[req.pid].row_hit_rate_write.Collect(1);
Stat.procs[req.pid].row_hit_write.Collect();
}
req.hit = 1;
// Power Measurement:
Sim.NVM_power_statistics(req.pid, req.migrated_request, req.type, true);
//
if (Config.proc.cache_insertion_policy == "PFA")
{
Measurement.NVMHitSetRowBufferChange(req);
}
}
// if (req.type == ReqType.RD && (!req.migrated_request) )
// Dbg.Assert(cmd.type == Cmd.TypeEnum.READ);
//issue command
if (Config.proc.cache_insertion_policy == "PFA")
{
Measurement.NVMSetCorePrevRowid(req);
}
issue_cmd(cmd);
}
