public static OpCodeInfo[] GetOpCodeInfos(OpCodeInfoOptions options) { Assert.True(options.Bitness == 16 || options.Bitness == 32 || options.Bitness == 64, $"Invalid bitness: {options.Bitness}"); var result = new List <OpCodeInfo>(); foreach (var code in (Code[])Enum.GetValues(typeof(Code))) { var opCode = code.ToOpCode(); if (!opCode.IsAvailableInMode(options.Bitness)) { continue; } // INVALID, db, dw, dd, dq if (!opCode.IsInstruction) { continue; } // These require a WAIT instruction, so ignore them. The no-wait instructions (eg. fnstenv) are tested if (opCode.Fwait) { continue; } if (!options.Filter.ShouldInclude(code, null)) { continue; } switch (opCode.Encoding) { case EncodingKind.Legacy: break; case EncodingKind.VEX: if (!options.IncludeVEX) { continue; } break; case EncodingKind.EVEX: if (!options.IncludeEVEX) { continue; } break; case EncodingKind.XOP: if (!options.IncludeXOP) { continue; } break; case EncodingKind.D3NOW: if (!options.Include3DNow) { continue; } break; default: throw ThrowHelpers.Unreachable; } switch (code) { // DecoderOptions.OldFpu case Code.Frstpm: case Code.Fstdw_AX: case Code.Fstsg_AX: continue; // DecoderOptions.Jmpe case Code.Jmpe_rm16: case Code.Jmpe_rm32: case Code.Jmpe_disp16: case Code.Jmpe_disp32: continue; // DecoderOptions.Pcommit case Code.Pcommit: continue; // DecoderOptions.Loadall286 case Code.Loadallreset286: case Code.Loadall286: continue; // DecoderOptions.Loadall386 case Code.Loadall386: continue; // DecoderOptions.Cl1invmb case Code.Cl1invmb: continue; // DecoderOptions.Umov case Code.Umov_rm8_r8: case Code.Umov_rm16_r16: case Code.Umov_rm32_r32: case Code.Umov_r8_rm8: case Code.Umov_r16_rm16: case Code.Umov_r32_rm32: continue; // DecoderOptions.MovTr case Code.Mov_r32_tr: case Code.Mov_tr_r32: continue; // DecoderOptions.Xbts case Code.Xbts_r16_rm16: case Code.Xbts_r32_rm32: case Code.Ibts_rm16_r16: case Code.Ibts_rm32_r32: continue; // DecoderOptions.Cmpxchg486A case Code.Cmpxchg486_rm8_r8: case Code.Cmpxchg486_rm16_r16: case Code.Cmpxchg486_rm32_r32: continue; // 8086 only case Code.Popw_CS: continue; // AMD only case Code.Ud0: if (options.CpuDecoder != CpuDecoder.AMD) { continue; } break; // Intel only case Code.Ud0_r16_rm16: case Code.Ud0_r32_rm32: case Code.Ud0_r64_rm64: if (options.CpuDecoder == CpuDecoder.AMD) { continue; } break; case Code.Call_rm16: case Code.Jmp_rm16: case Code.Jo_rel8_16: case Code.Jno_rel8_16: case Code.Jb_rel8_16: case Code.Jae_rel8_16: case Code.Je_rel8_16: case Code.Jne_rel8_16: case Code.Jbe_rel8_16: case Code.Ja_rel8_16: case Code.Js_rel8_16: case Code.Jns_rel8_16: case Code.Jp_rel8_16: case Code.Jnp_rel8_16: case Code.Jl_rel8_16: case Code.Jge_rel8_16: case Code.Jle_rel8_16: case Code.Jg_rel8_16: case Code.Jmp_rel8_16: case Code.Jo_rel16: case Code.Jno_rel16: case Code.Jb_rel16: case Code.Jae_rel16: case Code.Je_rel16: case Code.Jne_rel16: case Code.Jbe_rel16: case Code.Ja_rel16: case Code.Js_rel16: case Code.Jns_rel16: case Code.Jp_rel16: case Code.Jnp_rel16: case Code.Jl_rel16: case Code.Jge_rel16: case Code.Jle_rel16: case Code.Jg_rel16: case Code.Call_rel16: case Code.Jmp_rel16: case Code.Loopne_rel8_16_ECX: case Code.Loopne_rel8_16_RCX: case Code.Loope_rel8_16_ECX: case Code.Loope_rel8_16_RCX: case Code.Loop_rel8_16_ECX: case Code.Loop_rel8_16_RCX: case Code.Jecxz_rel8_16: case Code.Jrcxz_rel8_16: case Code.Retnw_imm16: case Code.Retnw: if (options.Bitness == 64) { // Only supported by AMD in 64-bit mode if (options.CpuDecoder != CpuDecoder.AMD) { continue; } } break; case Code.Call_m1664: case Code.Jmp_m1664: case Code.Lss_r64_m1664: case Code.Lfs_r64_m1664: case Code.Lgs_r64_m1664: if (options.Bitness == 64) { // Only supported by Intel in 64-bit mode if (options.CpuDecoder != CpuDecoder.Intel) { continue; } } break; } result.Add(opCode); } return(result.ToArray()); }
public static OpCodeInfo[] GetOpCodeInfos(OpCodeInfoOptions options) { Assert.True(options.Bitness == 16 || options.Bitness == 32 || options.Bitness == 64, $"Invalid bitness: {options.Bitness}"); var result = new List <OpCodeInfo>(); foreach (var code in (Code[])Enum.GetValues(typeof(Code))) { var opCode = code.ToOpCode(); if (!opCode.IsAvailableInMode(options.Bitness)) { continue; } // INVALID, db, dw, dd, dq if (!opCode.IsInstruction) { continue; } // These require a WAIT instruction, so ignore them. The no-wait instructions (eg. fnstenv) are tested if (opCode.Fwait) { continue; } if (!options.Filter.ShouldInclude(code, null)) { continue; } switch (opCode.Encoding) { case EncodingKind.Legacy: break; case EncodingKind.VEX: if (!options.IncludeVEX) { continue; } break; case EncodingKind.EVEX: if (!options.IncludeEVEX) { continue; } break; case EncodingKind.XOP: if (!options.IncludeXOP) { continue; } break; case EncodingKind.D3NOW: if (!options.Include3DNow) { continue; } break; default: throw ThrowHelpers.Unreachable; } switch (code) { // DecoderOptions.OldFpu case Code.Frstpm: case Code.Fnstdw_AX: case Code.Fstdw_AX: case Code.Fnstsg_AX: case Code.Fstsg_AX: continue; // DecoderOptions.Jmpe case Code.Jmpe_rm16: case Code.Jmpe_rm32: case Code.Jmpe_disp16: case Code.Jmpe_disp32: continue; // DecoderOptions.Pcommit case Code.Pcommit: continue; // DecoderOptions.Loadall286 case Code.Loadallreset286: case Code.Loadall286: continue; // DecoderOptions.Loadall386 case Code.Loadall386: continue; // DecoderOptions.Cl1invmb case Code.Cl1invmb: continue; // DecoderOptions.Umov case Code.Umov_rm8_r8: case Code.Umov_rm16_r16: case Code.Umov_rm32_r32: case Code.Umov_r8_rm8: case Code.Umov_r16_rm16: case Code.Umov_r32_rm32: continue; // DecoderOptions.MovTr case Code.Mov_r32_tr: case Code.Mov_tr_r32: continue; // DecoderOptions.Xbts case Code.Xbts_r16_rm16: case Code.Xbts_r32_rm32: case Code.Ibts_rm16_r16: case Code.Ibts_rm32_r32: continue; // DecoderOptions.Cmpxchg486A case Code.Cmpxchg486_rm8_r8: case Code.Cmpxchg486_rm16_r16: case Code.Cmpxchg486_rm32_r32: continue; // DecoderOptions.Cyrix case Code.Rdshr_rm32: case Code.Wrshr_rm32: case Code.Smint: case Code.Svdc_m80_Sreg: case Code.Rsdc_Sreg_m80: case Code.Svldt_m80: case Code.Rsldt_m80: case Code.Svts_m80: case Code.Rsts_m80: case Code.Bb0_reset: case Code.Bb1_reset: case Code.Cpu_write: case Code.Cpu_read: case Code.Paveb_mm_mmm64: case Code.Paddsiw_mm_mmm64: case Code.Pmagw_mm_mmm64: case Code.Pdistib_mm_m64: case Code.Psubsiw_mm_mmm64: case Code.Pmvzb_mm_m64: case Code.Pmulhrw_mm_mmm64: case Code.Pmvnzb_mm_m64: case Code.Pmvlzb_mm_m64: case Code.Pmvgezb_mm_m64: case Code.Pmulhriw_mm_mmm64: case Code.Pmachriw_mm_m64: case Code.Cyrix_D9D7: case Code.Cyrix_D9E2: case Code.Ftstp: case Code.Cyrix_D9E7: case Code.Frint2: case Code.Frichop: case Code.Cyrix_DED8: case Code.Cyrix_DEDA: case Code.Cyrix_DEDC: case Code.Cyrix_DEDD: case Code.Cyrix_DEDE: case Code.Frinear: continue; // DecoderOptions.Cyrix_DMI case Code.Dmint: case Code.Rdm: continue; // DecoderOptions.Cyrix_SMINT_0F7E case Code.Smint_0F7E: continue; // DecoderOptions.ALTINST case Code.Altinst: continue; // 8086 only case Code.Popw_CS: continue; // AMD only case Code.Ud0: if (options.CpuDecoder != CpuDecoder.AMD) { continue; } break; // Intel only case Code.Ud0_r16_rm16: case Code.Ud0_r32_rm32: case Code.Ud0_r64_rm64: if (options.CpuDecoder == CpuDecoder.AMD) { continue; } break; case Code.Call_rm16: case Code.Jmp_rm16: case Code.Jo_rel8_16: case Code.Jno_rel8_16: case Code.Jb_rel8_16: case Code.Jae_rel8_16: case Code.Je_rel8_16: case Code.Jne_rel8_16: case Code.Jbe_rel8_16: case Code.Ja_rel8_16: case Code.Js_rel8_16: case Code.Jns_rel8_16: case Code.Jp_rel8_16: case Code.Jnp_rel8_16: case Code.Jl_rel8_16: case Code.Jge_rel8_16: case Code.Jle_rel8_16: case Code.Jg_rel8_16: case Code.Jmp_rel8_16: case Code.Jo_rel16: case Code.Jno_rel16: case Code.Jb_rel16: case Code.Jae_rel16: case Code.Je_rel16: case Code.Jne_rel16: case Code.Jbe_rel16: case Code.Ja_rel16: case Code.Js_rel16: case Code.Jns_rel16: case Code.Jp_rel16: case Code.Jnp_rel16: case Code.Jl_rel16: case Code.Jge_rel16: case Code.Jle_rel16: case Code.Jg_rel16: case Code.Call_rel16: case Code.Jmp_rel16: case Code.Loopne_rel8_16_ECX: case Code.Loopne_rel8_16_RCX: case Code.Loope_rel8_16_ECX: case Code.Loope_rel8_16_RCX: case Code.Loop_rel8_16_ECX: case Code.Loop_rel8_16_RCX: case Code.Jecxz_rel8_16: case Code.Jrcxz_rel8_16: case Code.Retnw_imm16: case Code.Retnw: if (options.Bitness == 64) { // Only supported by AMD in 64-bit mode if (options.CpuDecoder != CpuDecoder.AMD) { continue; } } break; case Code.Call_m1664: case Code.Jmp_m1664: case Code.Lss_r64_m1664: case Code.Lfs_r64_m1664: case Code.Lgs_r64_m1664: if (options.Bitness == 64) { // Only supported by Intel in 64-bit mode if (options.CpuDecoder != CpuDecoder.Intel) { continue; } } break; } result.Add(opCode); } return(result.ToArray()); }
public static OpCodeInfo[] GetOpCodeInfos(OpCodeInfoOptions options) { Assert.True(options.Bitness == 16 || options.Bitness == 32 || options.Bitness == 64, $"Invalid bitness: {options.Bitness}"); var result = new List <OpCodeInfo>(); foreach (var code in (Code[])Enum.GetValues(typeof(Code))) { var opCode = code.ToOpCode(); if (!opCode.IsAvailableInMode(options.Bitness)) { continue; } // INVALID, db, dw, dd, dq if (!opCode.IsInstruction) { continue; } // These require a WAIT instruction, so ignore them. The no-wait instructions (eg. fnstenv) are tested if (opCode.Fwait) { continue; } if (!options.Filter.ShouldInclude(code)) { continue; } switch (opCode.Encoding) { case EncodingKind.Legacy: break; case EncodingKind.VEX: if (!options.IncludeVEX) { continue; } break; case EncodingKind.EVEX: if (!options.IncludeEVEX) { continue; } break; case EncodingKind.XOP: if (!options.IncludeXOP) { continue; } break; case EncodingKind.D3NOW: if (!options.Include3DNow) { continue; } break; case EncodingKind.MVEX: if (!options.IncludeMVEX) { continue; } break; default: throw ThrowHelpers.Unreachable; } var decOpt = opCode.DecoderOption; if (decOpt != DecoderOptions.None && decOpt != DecoderOptions.MPX) { continue; } // 8086 only if (code == Code.Popw_CS) { continue; } switch (options.CpuDecoder) { case CpuDecoder.Intel: switch (options.Bitness) { case 16: if (!opCode.IntelDecoder16) { continue; } break; case 32: if (!opCode.IntelDecoder32) { continue; } break; case 64: if (!opCode.IntelDecoder64) { continue; } break; default: throw ThrowHelpers.Unreachable; } break; case CpuDecoder.AMD: switch (options.Bitness) { case 16: if (!opCode.AmdDecoder16) { continue; } break; case 32: if (!opCode.AmdDecoder32) { continue; } break; case 64: if (!opCode.AmdDecoder64) { continue; } break; default: throw ThrowHelpers.Unreachable; } break; default: throw ThrowHelpers.Unreachable; } result.Add(opCode); } return(result.ToArray()); }