// public bool[] schedMask;
// public int[] bank_reserve;
// public int data_bus_reserved_priority;
// public bool[] bank_reserved_rowhit;
public DualSlackSchedule(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
top_index_in_buf = new int[Config.Ng];
oldest_when_arrived = new ulong[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
if( bw_required == null )
bw_required = new int[Config.Ng];
if( bw_allocated == null )
bw_allocated = new int[Config.Ng];
if( bw_consumed == null )
bw_consumed = new int[Config.Ng];
if( rank == null )
rank = new int[Config.Ng];
bw_consumed_per_sched = new int[Config.Ng];
if( shared_req_per_core == 0 )
get_effective_req_sum();
priority = new int[Config.Ng];
// schedMask = new bool[Config.Ng];
// bank_reserve = new int[Config.memory.numBanks];
// bank_reserved_rowhit = new bool[Config.memory.numBanks];
// data_bus_reserved_priority = 0;
}
public SchedTCMwithPriorHWA(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service = new double[Config.Ng];
curr_service = new double[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
rbl = new double[Config.Ng];
shadow_row_hits = new ulong[Config.Ng];
blp = new double[Config.Ng];
blp_sample_sum = new uint[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
nice = new int[Config.Ng];
shuffle_cycles_left = Config.sched.shuffle_cycles;
this.chan = chan;
log_cnt = 0;
req_num = new int[Config.Ng];
buf_num = new int[Config.Ng];
hwa_prior = new int[Config.HWANum];
memreq_cnt = new int[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
memreq_cnt[i] = 0;
}
public SchedGPARBS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
bankLoad = new int[Config.Ng,Config.memory.numRanks,Config.memory.numBanks];
maxBankLoad = new int[Config.Ng];
totalLoad = new int[Config.Ng];
overallRank = new int[Config.Ng];
}
// public bool[] schedMask;
// public int[] bank_reserve;
// public int data_bus_reserved_priority;
// public bool[] bank_reserved_rowhit;
public SchedFRFCFSDeadLine(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
hwa_prior = new int[Config.HWANum];
deadline_prior = new int[Config.Ng];
// schedMask = new bool[Config.Ng];
// bank_reserve = new int[Config.memory.numBanks];
// bank_reserved_rowhit = new bool[Config.memory.numBanks];
// data_bus_reserved_priority = 0;
}
public ATLAS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
curr_service = new double[Config.Ng];
service = new double[Config.Ng];
this.chan = chan;
quantum_cycles_left = Config.sched.quantum_cycles;
}
public Bank(int index, DRAM mem, Channel chan, Rank rank)
{
this.index = index;
this.mem = mem;
this.chan = chan;
this.rank = rank;
cRAS = Config.memory.cRAS;
cCAS = Config.memory.cCAS;
cWR = Config.memory.cWR;
cDQS = Config.memory.cDQS;
cWTR = Config.memory.cWTR;
cRCD = Config.memory.cRCD;
cRP = Config.memory.cRP;
cRTP = Config.memory.cRTP;
cRC = Config.memory.cRC;
cRRD = Config.memory.cRRD;
}
public SchedTCMDeadLine(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service = new double[Config.Ng];
curr_service = new double[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
rbl = new double[Config.Ng];
shadow_row_hits = new ulong[Config.Ng];
blp = new double[Config.Ng];
blp_sample_sum = new uint[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
nice = new int[Config.Ng];
shuffle_cycles_left = Config.sched.shuffle_cycles;
this.chan = chan;
Console.WriteLine("TCM Parameter Quantum:{0}, shuffle:{1}", quantum_cycles_left, shuffle_cycles_left );
Console.WriteLine("Exception Check!!");
catchflag = 0;
hwa_prior = new int[Config.HWANum];
deadline_prior = new int[Config.Ng];
mem_intensity_req_cnt = new int[Config.Ng];
mem_nonintensity_req_cnt = new int[Config.Ng];
next_cnt_disable = new bool[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
{
mem_intensity_req_cnt[i] = 0;
mem_nonintensity_req_cnt[i] = 0;
next_cnt_disable[i] = false;
}
}
public SchedTCM(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service = new double[Config.Ng];
curr_service = new double[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
rbl = new double[Config.Ng];
shadow_row_hits = new ulong[Config.Ng];
blp = new double[Config.Ng];
blp_sample_sum = new uint[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
nice = new int[Config.Ng];
shuffle_cycles_left = Config.sched.shuffle_cycles;
this.chan = chan;
}
public SchedInvMPKI(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
mpki = new double[Config.Ng];
}
public SchedFRFCFS_PrioCPUWhenNonBursty(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
ch = chan;
}
public SchedBLP(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
}
// checkQueueingDelay will check how long is the request queues in each channel.
// returns true if it is lone and should enable batching; otw, returns false
public bool checkQueueingDelay(Channel chan)
{
int sum = 0;
for(int i=0;i<chan.buf.Length;i++)
{
if(chan.buf[i].Valid) sum++;
}
if(sum > Config.triggerBatchingThresh) return true;
else return false;
}
public SchedInvFRFCFS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
}
public SchedTCMClusterOptProb4(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service = new double[Config.Ng];
curr_service = new double[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
rbl = new double[Config.Ng];
shadow_row_hits = new ulong[Config.Ng];
blp = new double[Config.Ng];
blp_sample_sum = new uint[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
nice = new int[Config.Ng];
shuffle_cycles_left = Config.sched.shuffle_cycles;
this.chan = chan;
Console.WriteLine("TCM Parameter Quantum:{0}, shuffle:{1}", quantum_cycles_left, shuffle_cycles_left );
Console.WriteLine("Exception Check!!");
catchflag = 0;
hwa_prior = new int[Config.HWANum];
deadline_prior = new int[Config.Ng];
cRandom = new System.Random();
mem_intensity_req_cnt = new int[Config.Ng];
mem_nonintensity_req_cnt = new int[Config.Ng];
next_cnt_disable = new bool[Config.Ng];
memreq_cnt = new int[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
memreq_cnt[i] = 0;
for( int i = 0; i < Config.Ng; i++ )
{
mem_intensity_req_cnt[i] = 0;
mem_nonintensity_req_cnt[i] = 0;
next_cnt_disable[i] = false;
}
cluster_factor = Config.sched.AS_cluster_factor;
pre_req_num = new ulong[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
{
pre_req_num[i] = 0;
}
accelerate_probability_nonint = new int[Config.Ng];
accelerate_probability_int = new int[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
{
accelerate_probability_nonint[i] = Config.sched.accelerate_probability_nonint;
accelerate_probability_int[i] = Config.sched.accelerate_probability_int;
}
quantum_cycles_for_probability = Config.sched.quantum_cycles_for_probability;
quantum_cycles_left_for_probability = Config.sched.quantum_cycles_for_probability;
quantum_cycles_for_suspend = Config.sched.quantum_cycles_for_suspend;
quantum_cycles_left_for_suspend = 0;
bw_shortage_cnt = 0;
}
public DRAM(Channel chan)
{
this.chan = chan;
numRanks = Config.memory.numRanks;
numBanks = Config.memory.numBanks;
busWidth = Config.memory.busWidth;
busRatio = Config.memory.busRatio;
ranks = new Rank[numRanks];
for(int i=0;i<numRanks;i++)
ranks[i] = new Rank(i,this,chan);
dataBus = new ulong[20]; // this covers 64*Length bus cycles into the future
for(int i=0;i<dataBus.Length;i++)
dataBus[i] = 0;
}
public Rank(int index, DRAM mem, Channel chan)
{
this.index = index;
this.mem = mem;
this.chan = chan;
numBanks = Config.memory.numBanks;
banks = new Bank[numBanks];
for(int i=0;i<numBanks;i++)
banks[i] = new Bank(i,mem,chan,this);
}
/**
* Constructor
*/
public MemCtlr(Node node)
{
this.node = node;
//memory id
mem_id = index++;
//per-channel state
numChannels = Config.memory.numChannels;
numRanks = Config.memory.numRanks;
numBanks = Config.memory.numBanks;
this.triggerBatching = new bool[numChannels];
for(int i=0;i<numChannels;i++)
triggerBatching[i] = false;
/* HWA CODE */
// queueFromCores = new Queue<MemoryRequest>[numChannels];
// for(int i=0;i<numChannels;i++)
// queueFromCores[i] = new Queue<MemoryRequest>();
queueFromCores = new List<MemoryRequest>[numChannels];
for(int i=0;i<numChannels;i++)
queueFromCores[i] = new List<MemoryRequest>();
/* HWA CODE */
channels = new Channel[numChannels];
for(int i=0;i<numChannels;i++)
channels[i] = new Channel(mem_id,i);
reRandomizeCountdown = randomizationInterval;
randomizer = new Random();
}
public Scheduler(SchedBuf[] buf, DRAM mem, Channel chan)
{
this.buf = buf;
this.mem = mem;
this.chan = chan;
schedMask = new bool[Config.Ng];
bank_reserve = new int[Config.memory.numBanks];
bank_reserve_priority = new int[Config.memory.numBanks];
bank_reserved_rowhit = new bool[Config.memory.numBanks];
data_bus_reserved_priority = 0;
}
public SchedFRFCFS_PrioCPU(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
}
public SchedFRFCFSwithPriorHWA (SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
hwa_prior = new int[Config.HWANum];
}
