public Node(NodeMapping mapping, Coord c)
{
m_coord = c;
m_mapping = mapping;
if (mapping.hasCPU(c.ID))
{
m_cpu = new CPU(this);
}
if (mapping.hasMem(c.ID))
{
Console.WriteLine("Proc/Node.cs : MC locations:{0}", c.ID);
m_mem = new MemCtlr(this);
}
m_inj_pool = Simulator.controller.newPrioPktPool(m_coord.ID);
Simulator.controller.setInjPool(m_coord.ID, m_inj_pool);
m_injQueue_flit = new Queue<Flit>();
m_injQueue_evict = new Queue<Flit>();
m_local = new Queue<Packet>();
m_rxbuf_naive = new RxBufNaive(this,
delegate(Flit f) { m_injQueue_evict.Enqueue(f); },
delegate(Packet p) { receivePacket(p); });
}
public GPUWindow(CPU cpu) : base(cpu) {
m_cpu = cpu;
next = oldest = 0;
addresses = new ulong[Config.proc.GPUWindowSize];
writes = new bool[Config.proc.GPUWindowSize];
requests = new Request[Config.proc.GPUWindowSize];
issueT = new ulong[Config.proc.GPUWindowSize];
headT = new ulong[Config.proc.GPUWindowSize];
ready = new bool[Config.proc.GPUWindowSize];
for (int i = 0; i < Config.proc.GPUWindowSize; i++) {
addresses[i] = NULL_ADDRESS;
writes[i] = false;
ready[i] = true;
requests[i] = null;
}
outstandingReqs = 0;
readLog = writeLog = false;
#if LOG
if (Simulator.sources.soloMode && Simulator.sources.solo.ID == procID)
{
sw = new StreamWriter ("insn.log");
sw.WriteLine("# cycle instrNr req_seq bank netlat injlat");
}
else
sw = null;
#endif
}
public InstructionWindow(CPU cpu) {
m_cpu = cpu;
next = oldest = 0;
addresses = new ulong[Config.proc.instWindowSize];
writes = new bool[Config.proc.instWindowSize];
ready = new bool[Config.proc.instWindowSize];
requests = new Request[Config.proc.instWindowSize];
issueT = new ulong[Config.proc.instWindowSize];
headT = new ulong[Config.proc.instWindowSize];
/* HWA CODE */
dram_req = new bool[Config.proc.instWindowSize];
m_match_mask = ~ ( ((ulong)1 << Config.cache_block) - 1 );
for (int i = 0; i < Config.proc.instWindowSize; i++) {
addresses[i] = NULL_ADDRESS;
writes[i] = false;
ready[i] = false;
requests[i] = null;
}
outstandingReqs = 0;
readLog = writeLog = false;
if (Config.writelog != "" && Config.writelog_node == cpu.node.coord.ID)
SetWrite(Config.writelog);
if (Config.readlog != "")
{
if (Config.readlog.StartsWith("auto"))
{
string prefix = Config.readlog.StartsWith("auto_") ?
Config.readlog.Substring(5) :
Config.router.algorithm.ToString();
SetRead(Simulator.network.workload.getLogFile(cpu.node.coord.ID, prefix));
}
else
SetRead(Config.readlog.Split(' ')[cpu.node.coord.ID]);
}
#if LOG
if (Simulator.sources.soloMode && Simulator.sources.solo.ID == procID)
{
sw = new StreamWriter ("insn.log");
sw.WriteLine("# cycle instrNr req_seq bank netlat injlat");
}
else
sw = null;
#endif
}
public Node(NodeMapping mapping, Coord c)
{
m_coord = c;
m_mapping = mapping;
if (mapping.hasCPU(c.ID))
{
m_cpu = new CPU(this);
}
if (mapping.hasMem(c.ID))
{
Console.WriteLine("Proc/Node.cs : MC locations:{0}", c.ID);
m_mem = new MemCtlr(this);
}
m_inj_pool = Simulator.controller.newPrioPktPool(m_coord.ID);
Simulator.controller.setInjPool(m_coord.ID, m_inj_pool);
m_injQueue_flit = new Queue<Flit>();
m_injQueue_evict = new Queue<Flit>();
m_injQueue_multi_flit = new Queue<Flit> [Config.sub_net];
for (int i=0; i<Config.sub_net; i++)
m_injQueue_multi_flit[i] = new Queue<Flit> ();
m_local = new Queue<Packet>();
//m_inheritance_table = new ArrayList();
m_inheritance_dict = new Dictionary<string, int> ();
m_rxbuf_naive = new RxBufNaive(this,
delegate(Flit f) { m_injQueue_evict.Enqueue(f); },
delegate(Packet p) { receivePacket(p); });
}
