public ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch)
{
var cmd = new StringBuilder();
if (PartName != null)
cmd.Append(" -p " + PartName);
foreach (var dir in SearchDirs)
cmd.Append(" -sd " + dir);
foreach (var lib in Libraries)
cmd.Append(" -l " + lib);
if (RulesFile != null)
cmd.Append(" -ur " + RulesFile);
if (IntermediateDir != null)
cmd.Append(" -dd " + IntermediateDir);
cmd.Append(" -nt ");
switch (NGOGeneration)
{
case ENGOGeneration.Off:
cmd.Append(" off");
break;
case ENGOGeneration.On:
cmd.Append(" on");
break;
case ENGOGeneration.Timestamp:
cmd.Append(" timestamp");
break;
}
if (UserConstraintsFile != null)
cmd.Append(" -uc " + UserConstraintsFile);
if (IgnoreLocationConstraints)
cmd.Append(" -r");
if (AllowUnmatchedLOCConstraints)
cmd.Append(" -aul");
if (AllowUnmatchedTimingGroupConstraints)
cmd.Append(" -aut");
if (InferPadComponents)
cmd.Append(" -a");
if (IgnoreDefaultUCF)
cmd.Append(" -i");
if (AllowUnexpandedBlocks)
cmd.Append(" -u");
if (InsertKeepHierarchy)
cmd.Append(" -insert_keep_hierarchy");
if (BMMFile != null)
cmd.Append(" -bm " + BMMFile);
if (FilterFile != null)
cmd.Append(" -filter " + FilterFile);
cmd.Append(" -intstyle silent");
if (Quiet)
cmd.Append(" -quiet");
if (Verbose)
cmd.Append(" -verbose");
cmd.Append(" " + DesignName);
if (NGDFile != null)
cmd.Append(" " + NGDFile);
return proj.AddToolToBatch(batch, proj.ProjectPath, "ngdbuild", cmd.ToString());
}
private void CopyEDKFiles(string ipRoot, string libName, XilinxProject xproj)
{
string libRoot = Path.Combine(ipRoot, libName, "hdl", "vhdl");
string[] files = Directory.GetFiles(libRoot, "*.vhd");
foreach (string filePath in files)
{
string file = Path.GetFileName(filePath);
CopyEDKFile(libRoot, file, libName, xproj);
}
}
static void Main(string[] args)
{
///default values
int cycles = 100;
FixedPointSettings.GlobalDefaultRadix = 10;
FixedPointSettings.GlobalOverflowMode = EOverflowMode.Fail;
///elaborate
SimpleCounterTestbench tb = new SimpleCounterTestbench();
DesignContext.Instance.Elaborate();
///print out config
Console.WriteLine("#cycles: " + cycles);
///simulate
DesignContext.Instance.Simulate(cycles * SimpleCounterTestbench.ClockPeriod);
///notify completion
Console.WriteLine("Done. [ #cycles = " + cycles + " ]");
#if RUNANALYSIS
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "SimpleCounter");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
//XilinxProject project_SC = new XilinxProject(@".\SystemC_output", "SimpleCounter");
//project_SC.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
//project_SC.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
//project_SC.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
//project_SC.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
//project_SC.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
//SystemCGenerator codeGen_SC = new SystemCGenerator();
//SynthesisEngine.Create(DesignContext.Instance, project_SC).Synthesize(codeGen_SC);
//project_SC.Save();
#endif
}
protected override void OnSynthesis(ISynthesisContext ctx)
{
if (!(ctx.Project is XilinxProject))
{
throw new InvalidOperationException("This floating point block can only be synthesized within the context of a Xilinx ISE project.");
}
XilinxProject xproj = (XilinxProject)ctx.Project;
string name = ctx.CodeGen.GetComponentID(Descriptor);
ComponentName = name;
CoreGenDescription cgproj, xco;
xproj.AddNewCoreGenDescription(name, out cgproj, out xco);
xco.FromComponent(this);
xco.Store();
xproj.ExecuteCoreGen(xco.Path, cgproj.Path);
}
public ProcessPool.ToolBatch Execute(XilinxProject proj, string xcoPath, string projPath)
{
if (proj.SkipIPCoreSynthesis)
{
return(null);
}
//see: http://www.xilinx.com/itp/xilinx6/books/docs/cgn/cgn.pdf
projPath = Path.GetFullPath(projPath);
xcoPath = Path.GetFullPath(xcoPath);
string dir = Path.GetDirectoryName(projPath);
bool madeSubst = false;
char drivel = default(char);
string drive = null;
try
{
var batch = ProcessPool.Instance.CreateBatch();
if (projPath.Length >= 160)
{
drivel = SubstManager.Instance.AllocateDrive();
drive = drivel + ":";
batch.Add("subst ", drive + " " + dir);
dir = drive + "\\";
projPath = dir + Path.GetFileName(projPath);
madeSubst = true;
}
string arguments = "-b \"" + xcoPath + "\" -p \"" + projPath + "\"";
proj.AddToolToBatch(batch, dir, "coregen", arguments);
if (madeSubst)
{
batch.Add("subst", drive + " /D");
}
batch.Start();
return(batch);
}
finally
{
if (drivel != default(char))
{
SubstManager.Instance.ReleaseDrive(drivel);
}
}
}
internal static void FromProject(this CoreGenDescription desc, XilinxProject proj, EPropAssoc assoc)
{
PropertyBag pbag = proj.PBag.Copy(assoc);
if (assoc == EPropAssoc.CoreGenProj)
{
string fname = Path.GetFileNameWithoutExtension(desc.Path);
string wdir = "./tmp/" + fname + "/";
pbag.PutProperty(EXilinxProjectProperties.CoreGen_WorkingDirectory, wdir);
}
IList<PropDesc> allProps = PropEnum.EnumProps(typeof(EXilinxProjectProperties));
foreach (PropDesc pd in allProps)
{
if (!pd.IDs.ContainsKey(assoc))
continue;
object value = pbag.GetProperty((EXilinxProjectProperties)pd.EnumValue);
desc.Set(pd.IDs[assoc], PropEnum.ToString(value, assoc), value.GetType());
}
}
public static void Run()
{
DesignContext.Reset();
Mod2TestDesign td = new Mod2TestDesign(3, 10, 2);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_ALUTestDesign", "ALUTestDesign");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
var tb = new FileWriterTestbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(0.5, ETimeUnit.us));
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_WriteFile", "FileWriterDesign");
project.ISEVersion = EISEVersion._13_2;
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
static void Main(string[] args)
{
Testbench_XilinxAdderSubtracter tb = new Testbench_XilinxAdderSubtracter();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(100 * Testbench_XilinxAdderSubtracter.ClockPeriod);
//DesignContext.Instance.Simulate(10 * (Testbench_zaehler.DataWidth + 3) * Testbench_zaehler.ClockPeriod);
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "XilinxAdderSubtracter");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
public static void Run()
{
DesignContext.Reset();
ALUTestDesign td = new ALUTestDesign(8, 8, 2);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(0.5, ETimeUnit.us));
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_ALUTestDesign", "ALUTestDesign");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
internal static void FromProject(this CoreGenDescription desc, XilinxProject proj, EPropAssoc assoc)
{
PropertyBag pbag = proj.PBag.Copy(assoc);
if (assoc == EPropAssoc.CoreGenProj)
{
string fname = Path.GetFileNameWithoutExtension(desc.Path);
string wdir = "./tmp/" + fname + "/";
pbag.PutProperty(EXilinxProjectProperties.CoreGen_WorkingDirectory, wdir);
}
IList <PropDesc> allProps = PropEnum.EnumProps(typeof(EXilinxProjectProperties));
foreach (PropDesc pd in allProps)
{
if (!pd.IDs.ContainsKey(assoc))
{
continue;
}
object value = pbag.GetProperty((EXilinxProjectProperties)pd.EnumValue);
desc.Set(pd.IDs[assoc], PropEnum.ToString(value, assoc), value.GetType());
}
}
public static void Run()
{
Testbench tb = new Testbench();
DesignContext.Instance.Elaborate();
///remember start time
Start = System.DateTime.Now.Ticks;
DesignContext.Instance.Simulate(Cycles * Testbench.ClockCycle);
#if RUNANALYSIS
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "Arbiter");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project_SC = new XilinxProject(@".\SystemC_output", "SimpleCounter");
project_SC.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project_SC.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project_SC.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project_SC.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project_SC.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
SystemCGenerator codeGen_SC = new SystemCGenerator();
SynthesisEngine.Create(DesignContext.Instance, project_SC).Synthesize(codeGen_SC);
project_SC.Save();
#endif
}
public ProcessPool.Tool SaveToXSTScriptAndAddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch, string scriptPath, string logPath)
{
SaveToXSTScript(scriptPath);
return AddToBatch(proj, batch, scriptPath, logPath);
}
public static ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch, string scriptPath, string logPath)
{
string args = "-intstyle \"silent\" -ifn \"" + scriptPath + "\" -ofn \"" + logPath + "\"";
return proj.AddToolToBatch(batch, proj.ProjectPath, "xst", args);
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_PortAccess_Testbench tb = new TestHLS_PortAccess_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
DesignContext.Stop();
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_PortAccess", "TestHLS_PortAccess");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
}
public ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch)
{
var cmd = new StringBuilder();
if (PartName != null)
{
cmd.Append("-p " + PartName);
}
cmd.Append(" -ol \"" + PropEnum.ToString(PlacerEffort, EPropAssoc.MAP) + "\"");
if (PlacerExtraEffort != EPlacerExtraEffortMap.None)
{
throw new NotImplementedException();
}
cmd.Append(" -t " + StartingPlacerCostTable);
cmd.Append(" -logic_opt ");
if (CombinatorialLogicOptimization)
{
cmd.Append("\"on\"");
}
else
{
cmd.Append("\"off\"");
}
cmd.Append(" -register_duplication ");
cmd.Append("\"" + PropEnum.ToString(RegisterDuplication, EPropAssoc.MAP) + "\"");
cmd.Append(" -global_opt \"" + PropEnum.ToString(GlobalOptimization, EPropAssoc.MAP) + "\"");
cmd.Append(" -equivalent_register_removal ");
if (EquivalentRegisterRemoval)
{
cmd.Append("\"on\"");
}
else
{
cmd.Append("\"off\"");
}
if (IgnoreUserTimingConstraints)
{
cmd.Append(" -x");
}
if (TrimUnconnectedSignals)
{
cmd.Append(" -u");
}
if (IgnoreKeepHierarchy)
{
cmd.Append(" -ignore_keep_hierarchy");
}
#if false
//FIXME: Which architectures allow for this property?
cmd.Append(" -cm \"" + PropEnum.ToString(OptimizationStrategyCoverMode, EPropAssoc.MAP) + "\"");
#endif
if (GenerateDetailedMapReport)
{
cmd.Append(" -detail");
}
cmd.Append(" -ir \"" + PropEnum.ToString(UseRLOCConstraints, EPropAssoc.MAP) + "\"");
cmd.Append(" -pr \"" + PropEnum.ToString(PackIORegistersIntoIOBs, EPropAssoc.MAP) + "\"");
if (MaximumCompression)
{
cmd.Append(" -c");
}
cmd.Append(" -lc \"" + PropEnum.ToString(LUTCombining, EPropAssoc.MAP) + "\"");
if (MapSliceLogicIntoUnusedBlockRAMs)
{
cmd.Append(" -bp");
}
cmd.Append(" -power ");
if (PowerReduction)
{
cmd.Append("\"on\"");
}
else
{
cmd.Append("\"off\"");
}
if (PowerActivityFile != null)
{
cmd.Append(" -activityfile \"" + PowerActivityFile + "\"");
}
cmd.Append(" -mt \"" + MultiThreading + "\"");
if (Overwrite)
{
cmd.Append(" -w");
}
if (OutputFile != null)
{
cmd.Append(" -o \"" + OutputFile + "\"");
}
cmd.Append(" \"" + InputFile + "\"");
if (PRFFile != null)
{
cmd.Append(" " + PRFFile);
}
return(proj.AddToolToBatch(batch, proj.ProjectPath, "map", cmd.ToString()));
}
public ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch)
{
var cmd = new StringBuilder();
cmd.Append("-ol \"" + PropEnum.ToString(OverallEffortLevel, EPropAssoc.PAR) + "\"");
#if false
//FIXME: Supporting device families?
cmd.Append(" -pl \"" + PropEnum.ToString(PlacerEffortLevel, EPropAssoc.PAR) + "\"");
cmd.Append(" -rl \"" + PropEnum.ToString(RouterEffortLevel, EPropAssoc.PAR) + "\"");
#endif
if (ExtraEffortLevel != EExtraEffortLevel.None)
{
cmd.Append(" -xl \"" + PropEnum.ToString(ExtraEffortLevel, EPropAssoc.PAR) + "\"");
}
if (MultiThreading > 1)
{
cmd.Append(" -mt \"" + MultiThreading + "\"");
}
#if false
//FIXME: Supporting device families?
cmd.Append(" -t \"" + PlacerCostTableEntry + "\"");
#endif
if (KeepCurrentPlacement)
{
cmd.Append(" -p");
}
if (ReentrantRoute)
{
cmd.Append(" -k");
}
if (DontRunRouter)
{
cmd.Append(" -r");
}
if (Overwrite)
{
cmd.Append(" -w");
}
if (SmartGuideFile != null)
{
cmd.Append(" -smartguide \"" + SmartGuideFile + "\"");
}
if (IgnoreUserTimingConstraintsAutoGen)
{
cmd.Append(" -x");
}
if (NoPadReport)
{
cmd.Append(" -nopad");
}
cmd.Append(" -power \"" + PropEnum.ToString(PowerReduction, EPropAssoc.PAR) + "\"");
if (PowerActivityFile != null)
{
cmd.Append(" -activityfile \"" + PowerActivityFile + "\"");
}
if (FilterFile != null)
{
cmd.Append(" -filter \"" + FilterFile + "\"");
}
if (IgnoreUserTimingConstraintsNoGen)
{
cmd.Append(" -ntd");
}
cmd.Append(" -intstyle silent");
if (ISERepositoryFile != null)
{
cmd.Append(" -ise \"" + ISERepositoryFile + "\"");
}
if (FilterFile != null)
{
cmd.Append(" -filter \"" + FilterFile + "\"");
}
cmd.Append(" \"" + InputFile + "\"");
cmd.Append(" \"" + OutputFile + "\"");
if (PhysicalConstraintsFile != null)
{
cmd.Append(" \"" + PhysicalConstraintsFile + "\"");
}
return(proj.AddToolToBatch(batch, proj.ProjectPath, "par", cmd.ToString()));
batch.Add(proj.ISEBinPath, proj.ProjectPath, "par", cmd.ToString());
}
public static ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch, string scriptPath, string logPath)
{
string args = "-intstyle \"silent\" -ifn \"" + scriptPath + "\" -ofn \"" + logPath + "\"";
return(proj.AddToolToBatch(batch, proj.ProjectPath, "xst", args));
}
private void CreateUCF(XilinxProject proj)
{
string path = proj.AddFile(proj.ProjectName + ".ucf");
var sw = new StreamWriter(path);
foreach (var pin in PinList)
{
if (pin.AssociatedSignal == null)
continue;
string indexExpr = "";
if (pin.AssociatedIndex.Length > 0)
indexExpr = pin
.AssociatedIndex
.Select(i => "[" + i + "]")
.Aggregate((x, y) => x + y);
var sd = (ISignalOrPortDescriptor)((IDescriptive)pin.AssociatedSignal).Descriptor;
var pd = sd.AsSignalRef(SignalRef.EReferencedProperty.Instance)
.RelateToComponent(TopLevelComponent.Descriptor)
.Desc;
sw.WriteLine("NET \"{0}{1}\" LOC = {2};",
pd.Name, indexExpr, pin.Name);
}
foreach (IPortDescriptor pd in TopLevelComponent.Descriptor.GetPorts())
{
var sd = pd.BoundSignal;
if (sd == null)
continue;
var csa = sd.QueryAttribute<ClockSpecAttribute>();
if (csa == null)
continue;
sw.WriteLine("TIMESPEC TS_{0} = PERIOD \"{1}\" {2} {3};",
pd.Name, pd.Name, csa.Period.Value, csa.Period.Unit);
sw.WriteLine("NET \"{0}\" TNM_NET = \"{1}\";",
pd.Name, pd.Name);
}
sw.Close();
}
private void CopyEDKFile(string libRoot, string fileName, string libName, XilinxProject xproj)
{
string path = xproj.AddFile(fileName);
xproj.SetFileLibrary(fileName, libName);
File.Copy(Path.Combine(libRoot, fileName), path, true);
}
public static void RunTest()
{
DesignContext.Reset();
TestDesign1 td1 = new TestDesign1(3, 4);
FixedPointSettings.GlobalOverflowMode = EOverflowMode.Wrap;
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(20 * TestDesign1.ClockPeriod);
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_TestDesign1", "TestDesign1");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen); ;
project.Save();
DesignContext.Reset();
}
public ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch)
{
var cmd = new StringBuilder();
if (VerboseReport || ErrorReport)
{
if (VerboseReport)
cmd.Append("-v ");
else
cmd.Append("-e ");
cmd.Append(ReportLimit);
}
if (TimingReport)
{
cmd.Append(" -l " + TimingReportLimit);
}
if (ReportPathsPerEndpoint)
{
cmd.Append(" -n " + EndpointsLimit);
}
if (SpeedGrade > 0)
{
cmd.Append(" -s " + SpeedGrade);
}
if (AdvancedAnalysis)
{
cmd.Append(" -a");
}
if (ReportUnconstrainedPaths)
{
cmd.Append(" -u " + UnconstrainedPathsLimit);
}
if (ReportFile != null)
{
cmd.Append(" -o \"" + ReportFile + "\"");
}
if (StampFile != null)
{
cmd.Append(" -stamp \"" + StampFile + "\"");
}
if (TSIFile != null)
{
cmd.Append(" -tsi \"" + TSIFile + "\"");
}
if (XMLReportFile != null)
{
cmd.Append(" -xml \"" + XMLReportFile + "\"");
}
if (NoDatasheet)
{
cmd.Append(" -nodatasheet");
}
if (TimegroupsSection)
{
cmd.Append(" -timegroups");
}
if (ReportFastestPaths)
{
cmd.Append(" -fastpaths");
}
if (FilterFile != null)
{
cmd.Append(" -filter \"" + FilterFile + "\"");
}
if (TurnOffPackageFlightDelay)
{
cmd.Append(" -noflight");
}
cmd.Append(" -intstyle silent");
if (ISEProjectFile != null)
{
cmd.Append(" -ise \"" + ISEProjectFile + "\"");
}
cmd.Append(" \"" + PhysicalDesignFile + "\"");
if (PhysicalConstraintsFile != null)
cmd.Append(" \"" + PhysicalConstraintsFile + "\"");
if (UserConstraintsFile != null)
cmd.Append(" -ucf \"" + UserConstraintsFile + "\"");
return proj.AddToolToBatch(batch, proj.ProjectPath, "trce", cmd.ToString());
}
public ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch)
{
var cmd = new StringBuilder();
if (VerboseReport || ErrorReport)
{
if (VerboseReport)
{
cmd.Append("-v ");
}
else
{
cmd.Append("-e ");
}
cmd.Append(ReportLimit);
}
if (TimingReport)
{
cmd.Append(" -l " + TimingReportLimit);
}
if (ReportPathsPerEndpoint)
{
cmd.Append(" -n " + EndpointsLimit);
}
if (SpeedGrade > 0)
{
cmd.Append(" -s " + SpeedGrade);
}
if (AdvancedAnalysis)
{
cmd.Append(" -a");
}
if (ReportUnconstrainedPaths)
{
cmd.Append(" -u " + UnconstrainedPathsLimit);
}
if (ReportFile != null)
{
cmd.Append(" -o \"" + ReportFile + "\"");
}
if (StampFile != null)
{
cmd.Append(" -stamp \"" + StampFile + "\"");
}
if (TSIFile != null)
{
cmd.Append(" -tsi \"" + TSIFile + "\"");
}
if (XMLReportFile != null)
{
cmd.Append(" -xml \"" + XMLReportFile + "\"");
}
if (NoDatasheet)
{
cmd.Append(" -nodatasheet");
}
if (TimegroupsSection)
{
cmd.Append(" -timegroups");
}
if (ReportFastestPaths)
{
cmd.Append(" -fastpaths");
}
if (FilterFile != null)
{
cmd.Append(" -filter \"" + FilterFile + "\"");
}
if (TurnOffPackageFlightDelay)
{
cmd.Append(" -noflight");
}
cmd.Append(" -intstyle silent");
if (ISEProjectFile != null)
{
cmd.Append(" -ise \"" + ISEProjectFile + "\"");
}
cmd.Append(" \"" + PhysicalDesignFile + "\"");
if (PhysicalConstraintsFile != null)
{
cmd.Append(" \"" + PhysicalConstraintsFile + "\"");
}
if (UserConstraintsFile != null)
{
cmd.Append(" -ucf \"" + UserConstraintsFile + "\"");
}
return(proj.AddToolToBatch(batch, proj.ProjectPath, "trce", cmd.ToString()));
}
/// <summary>
/// Constructs a new instance.
/// </summary>
/// <param name="project">ISE project</param>
public ToolFlow(XilinxProject project)
{
Project = project;
XST = new XSTFlow();
NGDBuild = new NGDBuildFlow();
Map = new MAPFlow();
PAR = new PARFlow();
TRCE = new TRCEFlow();
}
public ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch)
{
var cmd = new StringBuilder();
if (PartName != null)
cmd.Append("-p " + PartName);
cmd.Append(" -ol \"" + PropEnum.ToString(PlacerEffort, EPropAssoc.MAP) + "\"");
if (PlacerExtraEffort != EPlacerExtraEffortMap.None)
throw new NotImplementedException();
cmd.Append(" -t " + StartingPlacerCostTable);
cmd.Append(" -logic_opt ");
if (CombinatorialLogicOptimization)
cmd.Append("\"on\"");
else
cmd.Append("\"off\"");
cmd.Append(" -register_duplication ");
cmd.Append("\"" + PropEnum.ToString(RegisterDuplication, EPropAssoc.MAP) + "\"");
cmd.Append(" -global_opt \"" + PropEnum.ToString(GlobalOptimization, EPropAssoc.MAP) + "\"");
cmd.Append(" -equivalent_register_removal ");
if (EquivalentRegisterRemoval)
cmd.Append("\"on\"");
else
cmd.Append("\"off\"");
if (IgnoreUserTimingConstraints)
cmd.Append(" -x");
if (TrimUnconnectedSignals)
cmd.Append(" -u");
if (IgnoreKeepHierarchy)
cmd.Append(" -ignore_keep_hierarchy");
#if false
//FIXME: Which architectures allow for this property?
cmd.Append(" -cm \"" + PropEnum.ToString(OptimizationStrategyCoverMode, EPropAssoc.MAP) + "\"");
#endif
if (GenerateDetailedMapReport)
cmd.Append(" -detail");
cmd.Append(" -ir \"" + PropEnum.ToString(UseRLOCConstraints, EPropAssoc.MAP) + "\"");
cmd.Append(" -pr \"" + PropEnum.ToString(PackIORegistersIntoIOBs, EPropAssoc.MAP) + "\"");
if (MaximumCompression)
cmd.Append(" -c");
cmd.Append(" -lc \"" + PropEnum.ToString(LUTCombining, EPropAssoc.MAP) + "\"");
if (MapSliceLogicIntoUnusedBlockRAMs)
cmd.Append(" -bp");
cmd.Append(" -power ");
if (PowerReduction)
cmd.Append("\"on\"");
else
cmd.Append("\"off\"");
if (PowerActivityFile != null)
cmd.Append(" -activityfile \"" + PowerActivityFile + "\"");
cmd.Append(" -mt \"" + MultiThreading + "\"");
if (Overwrite)
cmd.Append(" -w");
if (OutputFile != null)
cmd.Append(" -o \"" + OutputFile + "\"");
cmd.Append(" \"" + InputFile + "\"");
if (PRFFile != null)
cmd.Append(" " + PRFFile);
return proj.AddToolToBatch(batch, proj.ProjectPath, "map", cmd.ToString());
}
/// <summary>
/// Synthesizes the design.
/// </summary>
/// <param name="destPath">target path which will contain the generated files</param>
/// <param name="designName">name of the design</param>
/// <param name="info">ISE information</param>
/// <param name="twinProject">optional twin project</param>
/// <param name="step">what stages of the overall flow to execute</param>
/// <returns>the generated ISE project</returns>
public XilinxProject Synthesize(string destPath, string designName, ISEInfo info,
IProject twinProject = null, EFlowStep step = EFlowStep.HDLGenAndIPCores)
{
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(destPath, designName)
{
TwinProject = twinProject
};
project.ISEVersion = info.VersionTag;
if (info.Path == null)
project.SkipIPCoreSynthesis = true;
else
project.ISEBinPath = info.Path;
project.PutProperty(EXilinxProjectProperties.DeviceFamily, Device.GetFamily());
project.PutProperty(EXilinxProjectProperties.Device, Device);
project.PutProperty(EXilinxProjectProperties.Package, Package);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, SpeedGrade);
project.SetVHDLProfile();
if (!step.HasFlag(EFlowStep.IPCores))
project.SkipIPCoreSynthesis = true;
project.TopLevelComponent = TopLevelComponent.Descriptor;
CreateUCF(project);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(GetComponentSet(), codeGen);
project.Save();
if (step.HasFlag(EFlowStep.XST) ||
step.HasFlag(EFlowStep.NGDBuild) ||
step.HasFlag(EFlowStep.Map) ||
step.HasFlag(EFlowStep.PAR) ||
step.HasFlag(EFlowStep.TRCE))
{
var flow = project.ConfigureFlow(TopLevelComponent);
flow.Start(step);
}
return project;
}
public ProcessPool.Tool SaveToXSTScriptAndAddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch, string scriptPath, string logPath)
{
SaveToXSTScript(scriptPath);
return(AddToBatch(proj, batch, scriptPath, logPath));
}
public static void Run()
{
SimpleCounterTestbench tb = new SimpleCounterTestbench();
DesignContext.Instance.Elaborate();
///remember start time
Start = System.DateTime.Now.Ticks;
DesignContext.Instance.Simulate(Cycles * SimpleCounterTestbench.ClockPeriod);
#if RUNANALYSIS
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "SimpleCounter");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
#endif
}
public ProcessPool.ToolBatch Execute(XilinxProject proj, string xcoPath, string projPath)
{
if (proj.SkipIPCoreSynthesis)
return null;
//see: http://www.xilinx.com/itp/xilinx6/books/docs/cgn/cgn.pdf
projPath = Path.GetFullPath(projPath);
xcoPath = Path.GetFullPath(xcoPath);
string dir = Path.GetDirectoryName(projPath);
bool madeSubst = false;
char drivel = default(char);
string drive = null;
try
{
var batch = ProcessPool.Instance.CreateBatch();
if (projPath.Length >= 160)
{
drivel = SubstManager.Instance.AllocateDrive();
drive = drivel + ":";
batch.Add("subst ", drive + " " + dir);
dir = drive + "\\";
projPath = dir + Path.GetFileName(projPath);
madeSubst = true;
}
string arguments = "-b \"" + xcoPath + "\" -p \"" + projPath + "\"";
proj.AddToolToBatch(batch, dir, "coregen", arguments);
if (madeSubst)
{
batch.Add("subst", drive + " /D");
}
batch.Start();
return batch;
}
finally
{
if (drivel != default(char))
SubstManager.Instance.ReleaseDrive(drivel);
}
}
public ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch)
{
var cmd = new StringBuilder();
cmd.Append("-ol \"" + PropEnum.ToString(OverallEffortLevel, EPropAssoc.PAR) + "\"");
#if false
//FIXME: Supporting device families?
cmd.Append(" -pl \"" + PropEnum.ToString(PlacerEffortLevel, EPropAssoc.PAR) + "\"");
cmd.Append(" -rl \"" + PropEnum.ToString(RouterEffortLevel, EPropAssoc.PAR) + "\"");
#endif
if (ExtraEffortLevel != EExtraEffortLevel.None)
cmd.Append(" -xl \"" + PropEnum.ToString(ExtraEffortLevel, EPropAssoc.PAR) + "\"");
if (MultiThreading > 1)
cmd.Append(" -mt \"" + MultiThreading + "\"");
#if false
//FIXME: Supporting device families?
cmd.Append(" -t \"" + PlacerCostTableEntry + "\"");
#endif
if (KeepCurrentPlacement)
cmd.Append(" -p");
if (ReentrantRoute)
cmd.Append(" -k");
if (DontRunRouter)
cmd.Append(" -r");
if (Overwrite)
cmd.Append(" -w");
if (SmartGuideFile != null)
cmd.Append(" -smartguide \"" + SmartGuideFile + "\"");
if (IgnoreUserTimingConstraintsAutoGen)
cmd.Append(" -x");
if (NoPadReport)
cmd.Append(" -nopad");
cmd.Append(" -power \"" + PropEnum.ToString(PowerReduction, EPropAssoc.PAR) + "\"");
if (PowerActivityFile != null)
cmd.Append(" -activityfile \"" + PowerActivityFile + "\"");
if (FilterFile != null)
cmd.Append(" -filter \"" + FilterFile + "\"");
if (IgnoreUserTimingConstraintsNoGen)
cmd.Append(" -ntd");
cmd.Append(" -intstyle silent");
if (ISERepositoryFile != null)
cmd.Append(" -ise \"" + ISERepositoryFile + "\"");
if (FilterFile != null)
cmd.Append(" -filter \"" + FilterFile + "\"");
cmd.Append(" \"" + InputFile + "\"");
cmd.Append(" \"" + OutputFile + "\"");
if (PhysicalConstraintsFile != null)
cmd.Append(" \"" + PhysicalConstraintsFile + "\"");
return proj.AddToolToBatch(batch, proj.ProjectPath, "par", cmd.ToString());
batch.Add(proj.ISEBinPath, proj.ProjectPath, "par", cmd.ToString());
}
static void Main(string[] args)
{
Tesbernch_Multiplier tb = new Tesbernch_Multiplier();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(100 * Tesbernch_Multiplier.ClockPeriod);
//DesignContext.Instance.Simulate(10 * (testbench_XilinxMultiplier_.DataWidth + 3) * testbench_XilinxMultiplier_.ClockPeriod);
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "XilinxMultiplier");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
private void CopyEDKFiles(string ipRoot, string libName, XilinxProject xproj)
{
string libRoot = Path.Combine(ipRoot, libName, "hdl", "vhdl");
string[] files = Directory.GetFiles(libRoot, "*.vhd");
foreach (string filePath in files)
{
string file = Path.GetFileName(filePath);
CopyEDKFile(libRoot, file, libName, xproj);
}
}
static void Main(string[] args)
{
///default values
int cycles = 100;
///elaborate
SimpleCounterTestbench tb = new SimpleCounterTestbench();
DesignContext.Instance.Elaborate();
///print out config
Console.WriteLine("#cycles: " + cycles);
///simulate
DesignContext.Instance.Simulate(cycles * SimpleCounterTestbench.ClockPeriod);
///notify completion
Console.WriteLine("Done. [ #cycles = " + cycles + " ]");
#if RUNANALYSIS
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "SimpleCounter");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project_SC = new XilinxProject(@".\SystemC_output", "SimpleCounter");
project_SC.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project_SC.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project_SC.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project_SC.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project_SC.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
SystemCGenerator codeGen_SC = new SystemCGenerator();
SynthesisEngine.Create(DesignContext.Instance, project_SC).Synthesize(codeGen_SC);
project_SC.Save();
#endif
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_FPU_Testbench tb = new TestHLS_FPU_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(3.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_FPU", "TestHLS_FPU");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
var eng = SynthesisEngine.Create(
DesignContext.Instance, new DocumentationProject(@".\hdl_out_TestHLS_FPU\doc"));
}
public ProcessPool.Tool AddToBatch(XilinxProject proj, ProcessPool.ToolBatch batch)
{
var cmd = new StringBuilder();
if (PartName != null)
{
cmd.Append(" -p " + PartName);
}
foreach (var dir in SearchDirs)
{
cmd.Append(" -sd " + dir);
}
foreach (var lib in Libraries)
{
cmd.Append(" -l " + lib);
}
if (RulesFile != null)
{
cmd.Append(" -ur " + RulesFile);
}
if (IntermediateDir != null)
{
cmd.Append(" -dd " + IntermediateDir);
}
cmd.Append(" -nt ");
switch (NGOGeneration)
{
case ENGOGeneration.Off:
cmd.Append(" off");
break;
case ENGOGeneration.On:
cmd.Append(" on");
break;
case ENGOGeneration.Timestamp:
cmd.Append(" timestamp");
break;
}
if (UserConstraintsFile != null)
{
cmd.Append(" -uc " + UserConstraintsFile);
}
if (IgnoreLocationConstraints)
{
cmd.Append(" -r");
}
if (AllowUnmatchedLOCConstraints)
{
cmd.Append(" -aul");
}
if (AllowUnmatchedTimingGroupConstraints)
{
cmd.Append(" -aut");
}
if (InferPadComponents)
{
cmd.Append(" -a");
}
if (IgnoreDefaultUCF)
{
cmd.Append(" -i");
}
if (AllowUnexpandedBlocks)
{
cmd.Append(" -u");
}
if (InsertKeepHierarchy)
{
cmd.Append(" -insert_keep_hierarchy");
}
if (BMMFile != null)
{
cmd.Append(" -bm " + BMMFile);
}
if (FilterFile != null)
{
cmd.Append(" -filter " + FilterFile);
}
cmd.Append(" -intstyle silent");
if (Quiet)
{
cmd.Append(" -quiet");
}
if (Verbose)
{
cmd.Append(" -verbose");
}
cmd.Append(" " + DesignName);
if (NGDFile != null)
{
cmd.Append(" " + NGDFile);
}
return(proj.AddToolToBatch(batch, proj.ProjectPath, "ngdbuild", cmd.ToString()));
}
