protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); NetlistContainer netlistContainer = GetNetlistContainer(); foreach (XDLNet n in netlistContainer.Nets) { foreach (XDLPip pip in n.Pips) { Tile t = FPGA.FPGA.Instance.GetTile(pip.Location); if (!IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)) { continue; } foreach (Slice s in t.Slices) { bool inport = s.PortMapping.IsSliceInPort(new Port(pip.To)); bool outport = s.PortMapping.IsSliceOutPort(new Port(pip.To)); if ((inport | outport) && pip.To.Contains('_')) { NetPin pin = null; if (inport) { pin = new NetInpin(); } else { pin = new NetOutpin(); } string[] atoms = pip.To.Split('_'); pin.SlicePort = atoms[1]; if (netlistContainer.Instances.Any(i => i.SliceName.Equals(s.SliceName))) { // there should be only one instance on the slice XDLInstance inst = (XDLInstance)netlistContainer.Instances.First(i => i.SliceName.Equals(s.SliceName)); pin.InstanceName = inst.Name; } else { pin.InstanceName = s.SliceName; } bool pinExistsAlready = n.NetPins.FirstOrDefault(np => np.InstanceName.Equals(pin.InstanceName) && np.SlicePort.Equals(pin.SlicePort)) != null; if (!pinExistsAlready) { n.Add(pin); } } } } } }
protected override void DoCommandAction() { if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.Vivado) { return; } FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); NetlistContainer nlc = GetNetlistContainer(); int workload = GetNetsToDecomposeWithOutpin().Count(); int count = 0; List <XDLNet> newNets = new List <XDLNet>(); foreach (XDLNet net in GetNetsToDecomposeWithOutpin().Where(n => n.PRLink)) { ProgressInfo.Progress = ProgressStart + (int)((double)count++ / (double)workload * ProgressShare); Dictionary <string, List <XDLPip> > pipsToRemove = null; // decompose nets without outpin. // e.g., placing a module on connection macros wil remove outpins from certain I/O bar wires if (net.NetPins.Where(np => np is NetOutpin).Count() == 0) { pipsToRemove = new Dictionary <string, List <XDLPip> >(); foreach (XDLPip pip in net.Pips) { if (!pipsToRemove.ContainsKey(pip.Location)) { pipsToRemove.Add(pip.Location, new List <XDLPip>()); } pipsToRemove[pip.Location].Add(pip); } } else { bool antenna = net.IsAntenna(out pipsToRemove); } bool firstArc = true; // values are all non empty litst foreach (List <XDLPip> l in pipsToRemove.Values) { foreach (XDLPip pip in l) { if (firstArc) { firstArc = false; //this.OutputManager.WriteOutput("Decomposing net " + net.Name); } XDLNet arc = new XDLNet(net.Name + "_arc_" + pip.Location + "_" + pip.From + "_" + pip.To); //arc.AddComment("decomposed from net (with outpin) " + net.Name); // TODO what about attributes? arc.Add(pip); // move inpins List <NetPin> netPinsToRemove = new List <NetPin>(); foreach (NetPin netpin in net.NetPins.Where(np => np is NetInpin)) { XDLInstance inst = (XDLInstance)nlc.GetInstanceByName(netpin.InstanceName); Tile pipTile = FPGA.FPGA.Instance.GetTile(pip.Location); if (pipTile.TileKey.Equals(inst.TileKey)) { //netpin.Comment += "taken from " + net.Name; arc.Add(netpin); // store net pip for later removal as we may not change the collection during iterating over it netPinsToRemove.Add(netpin); } } // remove the inpins from the original net ... net.RemoveAllPinStatements(np => netPinsToRemove.Contains(np)); // ... and remove the arc from the original net newNets.Add(arc); } } // only invoke Remove once per net (blocker is very slow) net.Remove(p => PipFilter(p, pipsToRemove)); } // decompose blocker net foreach (XDLNet net in GetNetsToDecomposeWithoutOutpin()) { foreach (XDLPip pip in net.Pips) { XDLNet arc = new XDLNet(net.Name + "_arc_" + pip.Location + "_" + pip.From + "_" + pip.To); //arc.AddComment("decomposed from net (without outpin) " + net.Name); // TODO what about attributes? arc.Add(pip); newNets.Add(arc); } // remove all pips net.ClearPips(); } // add arcs foreach (XDLNet n in newNets) { nlc.Add(n); } }
protected override void DoCommandAction() { List <Expectation> expectations = new List <Expectation>(); string line = ""; TextReader tr = new StreamReader(ExpectFile); while ((line = tr.ReadLine()) != null) { if (!line.StartsWith("expect")) { continue; } string[] atoms = line.Split(' '); Expectation expectation = new Expectation(); expectation.Direction = atoms[1]; expectation.InstanceNamePart = atoms[2]; expectation.SliceName = atoms[3]; expectation.ExpectedPortName = atoms[4]; expectation.ExpectedIndex = int.Parse(atoms[6]); expectations.Add(expectation); } tr.Close(); NetlistContainer netlist = GetNetlistContainer(); foreach (XDLInstance inst in netlist.Instances) { foreach (Expectation expectation in expectations.Where(e => e.SliceName.Equals(inst.SliceName))) { expectation.InstanceChecked = true; } } // check whether the ports reside on the expected nets Regex netNameMatch = new Regex(NetnameRegexp, RegexOptions.Compiled); // check index (works for module) foreach (Expectation expectation in expectations.Where(e => e.ExpectedIndex > 0)) { // inst might be null for connection macros when checking the fused module XDLInstance inst = (XDLInstance)netlist.Instances.FirstOrDefault(i => i.SliceName.Equals(expectation.SliceName)); foreach (XDLNet net in netlist.Nets) { foreach (NetPin pin in net.NetPins.Where(np => np.GetDirection().Equals(expectation.Direction))) { bool portMatch = pin.SlicePort.Equals(expectation.ExpectedPortName) && (inst == null ? true : pin.InstanceName.Equals(inst.Name)); bool netMatch = net.Name.Contains("<" + expectation.ExpectedIndex + ">") || net.Name.Contains("(" + expectation.ExpectedIndex + ")") || net.Name.Contains("[" + expectation.ExpectedIndex + "]"); // some ports may be connected through the net "GLOBAL_LOGIC0" bool globalLogicNet = net.Name.StartsWith("GLOBAL_LOGIC"); if (portMatch && netMatch) { expectation.IndexChecked = true; break; } else if (portMatch && globalLogicNet) { OutputManager.WriteWarning("Index of expectation " + expectation + " machted using GLOBAL_LOGIC net " + net.Name); expectation.IndexChecked = true; break; } } if (expectation.IndexChecked) { break; } } } // check what? foreach (Expectation expectation in expectations) { XDLInstance inst = (XDLInstance)netlist.Instances.FirstOrDefault(i => i.SliceName.Equals(expectation.SliceName)); if (inst == null) { continue; } else { foreach (XDLNet net in netlist.Nets) { foreach (NetPin pin in net.NetPins) { if (pin.InstanceName.Equals(inst.Name) && pin.SlicePort.Equals(expectation.ExpectedPortName)) { expectation.PortNameChecked = true; expectation.NetNameChecked = netNameMatch.IsMatch(net.Name); break; } } if (expectation.PortNameChecked) { break; } } } } List <Expectation> missing = new List <Expectation>(); missing.AddRange(expectations.Where(e => !e.InstanceChecked || !e.PortNameChecked || !e.NetNameChecked || (e.ExpectedIndex > 0 && !e.IndexChecked))); foreach (Expectation expectation in missing) { OutputManager.WriteOutput("Could not satisfy expectation " + expectation); } }
private void m_treeView_NodeMouseClick(object sender, TreeNodeMouseClickEventArgs e) { if (!Objects.NetlistContainerManager.Instance.Contains(NetlistContainerName)) { return; } NetlistContainer nlc = Objects.NetlistContainerManager.Instance.Get(NetlistContainerName); int slices = 0; int dsp = 0; int bram = 0; // primitive if (e.Node.Tag != null) { m_txtInstanceCode.Clear(); if (!(e.Node.Tag is TreeNodeTag)) { } TreeNodeTag tag = (TreeNodeTag)e.Node.Tag; XDLInstance inst = tag.Instance; if (tag.Instance == null) { m_txtInstanceCode.AppendText("no primitive code available for hierarchy node"); foreach (TreeNode leave in e.Node.GetChildNodes()) { TreeNodeTag leaveTag = (TreeNodeTag)leave.Tag; XDLInstance leaveInstance = leaveTag.Instance; if (leaveInstance != null) { if (IdentifierManager.Instance.IsMatch(leaveInstance.Location, IdentifierManager.RegexTypes.CLB)) { slices += 1; } else if (IdentifierManager.Instance.IsMatch(leaveInstance.Location, IdentifierManager.RegexTypes.BRAM)) { dsp += 1; } else if (IdentifierManager.Instance.IsMatch(leaveInstance.Location, IdentifierManager.RegexTypes.DSP)) { bram += 1; } } } } else { m_txtInstanceCode.AppendText(inst.ToString()); if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.CLB)) { slices = 1; } else if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.BRAM)) { dsp = 1; } else if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.DSP)) { bram = 1; } } } m_lblSlices.Text = slices + " Slices"; m_lblBRAM.Text = bram + " BRAMs"; m_lblDSP.Text = dsp + " DSPs"; }
private void DeriveBlockingData(LibraryElement libElement) { //////////////////////////// // find LOGICIN and LOGICOUT foreach (XDLPort xdlPort in ((XDLContainer)libElement.Containter).Ports) { XDLInstance inst = (XDLInstance)libElement.Containter.GetInstanceByName(xdlPort.InstanceName); Tile clb = FPGA.FPGA.Instance.GetTile(inst.Location); Tile interconnectTile = FPGATypes.GetInterconnectTile(clb); Slice slice = clb.GetSliceByName(inst.SliceName); // true: in, false: out (no needed) Dictionary <uint, bool> portMapping = new Dictionary <uint, bool>(); foreach (Port inPort in slice.PortMapping.GetPorts(FPGATypes.PortDirection.In)) { portMapping.Add(inPort.NameKey, true); } // 1 store all ports we need to connect the switchmatrx with macro in ports foreach (Tuple <Port, Port> intArc in interconnectTile.SwitchMatrix.GetAllArcs()) { bool portFound = false; // find the arc that is driven by the xdlPort && make sure that we get the correct slice foreach (Location loc in Navigator.GetDestinations(interconnectTile, intArc.Item2).Where(l => l.Tile.Location.Equals(clb.Location))) { foreach (Port clbPort in clb.SwitchMatrix.GetDrivenPorts(loc.Pip).Where(drivenPort => portMapping.ContainsKey(drivenPort.NameKey) && drivenPort.Name.EndsWith(xdlPort.SlicePort))) { libElement.AddPortToBlock(interconnectTile, intArc.Item2); portFound = true; break; } if (portFound) { break; } } } // 2 store all ports we need to connect the macro out ports to the switch matrix (LOGICOUT\d+) // // find the arc that is driven by the xdlPort && make sure that we get the correct slice foreach (Tuple <Port, Port> arc in clb.SwitchMatrix.GetAllArcs().Where(a => slice.PortMapping.IsSliceOutPort(a.Item1) && a.Item1.Name.EndsWith(xdlPort.SlicePort))) { foreach (Location loc in Navigator.GetDestinations(clb, arc.Item2)) { libElement.AddPortToBlock(loc.Tile, loc.Pip); } } } //////////////////////////// // extract begin pips to block foreach (XDLNet net in libElement.Containter.Nets) { foreach (XDLPip pip in net.Pips) { libElement.AddPortToBlock(FPGA.FPGA.Instance.GetTile(pip.Location), new Port(pip.From)); libElement.AddPortToBlock(FPGA.FPGA.Instance.GetTile(pip.Location), new Port(pip.To)); } } // sideeffect, trigger calculation of slice number to reuse this macro on other devices foreach (XDLInstance inst in libElement.Containter.Instances) { inst.DeriveTileKeyAndSliceNumber(); } // CLB anchor if (((XDLContainer)libElement.Containter).ExplicitAnchorFound) { if (((XDLContainer)libElement.Containter).HasInstanceByName(((XDLContainer)libElement.Containter).Anchor)) { XDLInstance anchorInst = (XDLInstance)libElement.Containter.GetInstanceByName(((XDLContainer)libElement.Containter).Anchor); libElement.ResourceShape.Anchor.AnchorLocationX = anchorInst.LocationX; libElement.ResourceShape.Anchor.AnchorLocationY = anchorInst.LocationY; libElement.ResourceShape.Anchor.AnchorSliceName = anchorInst.SliceName; libElement.ResourceShape.Anchor.AnchorSliceNumber = anchorInst.SliceNumber; libElement.ResourceShape.Anchor.AnchorTileLocation = anchorInst.Location; } else { Slice anchorSlice = FPGA.FPGA.Instance.GetSlice(((XDLContainer)libElement.Containter).Anchor); libElement.ResourceShape.Anchor.AnchorLocationX = anchorSlice.ContainingTile.LocationX; libElement.ResourceShape.Anchor.AnchorLocationY = anchorSlice.ContainingTile.LocationY; libElement.ResourceShape.Anchor.AnchorSliceName = anchorSlice.SliceName; libElement.ResourceShape.Anchor.AnchorSliceNumber = 0; // see CutOffFromDesign libElement.ResourceShape.Anchor.AnchorTileLocation = anchorSlice.ContainingTile.Location; } } else { // TODO der Slot muss ausgewaehlt sein! SetResourceShapeInfo setCmd = new SetResourceShapeInfo(); setCmd.LibraryElementName = libElement.Name; CommandExecuter.Instance.Execute(setCmd); } }