/// <summary> /// Processor Construction Function /// </summary> /// <param name="insp_"> Shared Instruction Partitioner </param> /// <param name="pid_"> Processor ID</param> public PIMProc(ref InsPartition insp_, int pid_) { pid = pid_; ins_p = insp_; L1Cache = new Cache(true); // Shared_Cache = new Cache(config, true); ins_w = new InstructionWindow(Config.ins_w_size, pid); IPC = PIMConfigs.IPC; if (PIMConfigs.use_l1_cache) { cache_req_queue = new Queue <ProcRequest>(); } MSHR = new List <ProcRequest>(Config.mshr_size); cal_restrict = new Counter(Config.IPC, Config.IPC); mem_restrict = new Counter(1, 1); alu = new ALU(); tlb = new PageConverter(); if (PIMConfigs.writeback) { writeback_req = new List <ProcRequest>(); } //init callback read_callback = new ReadCallBack(handle_read_callback); write_callback = new WriteCallBack(handle_write_callback); }
public ExternalMemorySharp(ReadCallBack readBytesDelegate, WriteCallBack writeBytesDelegate, bool is64BitGame) { Is64BitGame = is64BitGame; PointerSize = Is64BitGame ? 0x8 : 0x4; ReadBytesCallBack = readBytesDelegate; WriteBytesCallBack = writeBytesDelegate; }
public static void Init(ReadCallBack readBytesDelegate, WriteCallBack writeBytesDelegate, bool is64BitMemory) { ReadBytesCallBack = readBytesDelegate; WriteBytesCallBack = writeBytesDelegate; Is64BitMemory = is64BitMemory; PointerSize = Is64BitMemory ? 0x8 : 0x4; IsInit = true; }
public void Write(LogItem aLogItem) { if (aLogItem != null) { if (logItems.InvokeRequired) { WriteCallBack d = new WriteCallBack(Write); logItems.Invoke(d, new object[] { aLogItem }); } else { logItems.SelectionColor = aLogItem.Status; logItems.AppendText(aLogItem.Message); } } }
public Adder_Conventional(int id_, ref InsPartition insp_) { this.id = id_; input_count = 2; output_count = 1; isp = insp_; //******************************************************** //** ** //** Stage 1-1: Load Data ** //** ** //******************************************************** var item_stage1 = new PIMStage_LoadData(this, 0); pipeline[0] = (item_stage1 as Stage); item_stage1 = null; //******************************************************** //** ** //** Stage 1-2: Load data ** //** ** //******************************************************** var item_stage2 = new PIMStage_LoadData(this, 1); pipeline[1] = item_stage2 as Stage; item_stage2 = null; //******************************************************** //** ** //** Stage 3: Calculation ** //** ** //******************************************************** var item_stage3 = new PIMStage_Computation(this, 2, latency_op); item_stage3.set_link(ref pipeline[0]); item_stage3.set_link(ref pipeline[1]); pipeline[2] = item_stage3 as Stage; //******************************************************** //** ** //** Stage 4: Write results back ** //** ** //******************************************************** var item_stage4 = new PIMStage_Store(this, 3); item_stage4.set_link(ref pipeline[2]); pipeline[3] = item_stage4 as Stage; //init callback read_callback = new ReadCallBack(handle_read_callback); write_callback = new WriteCallBack(handle_write_callback); }
/// <summary> /// Processor Construction Function /// </summary> /// <param name="insp_"> Shared Instruction Partitioner </param> /// <param name="pid_"> Processor ID</param> public Proc(ref InsPartition insp_, int pid_) { //passing parameters pid = pid_; ins_p = insp_; IPC = Config.IPC; //init private cache L1Cache = new Cache(false); //init instruction window ins_w = new InstructionWindow(Config.ins_w_size, pid); //queue init if (Config.use_cache) { cache_req_queue = new Queue <ProcRequest>(); } MSHR = new List <ProcRequest>(Config.mshr_size); if (Config.writeback) { writeback_req = new List <ProcRequest>(); } //restrict cal_restrict = new Counter(Config.IPC, Config.IPC); mem_restrict = new Counter(1, 1); //alu alu = new ALU(); //init callback read_callback = new ReadCallBack(handle_read_callback); write_callback = new WriteCallBack(handle_write_callback); ins_port = new InspCPUSlavePort("CPU Insrtuction Cache", PortManager.Allocate()); ins_port.owner = this; }