public static void VerilogSample() { Console.WriteLine("Hello World!"); // TODO: Implement Functionality Here Stream stream = new FileStream("mux_using_assign.v", FileMode.Open); StreamReader inputStream = new StreamReader(stream); AntlrInputStream input = new AntlrInputStream(inputStream.ReadToEnd()); Verilog2001Lexer lexer = new Verilog2001Lexer(input); CommonTokenStream tokens = new CommonTokenStream(lexer); Verilog2001Parser parser = new Verilog2001Parser(tokens); IParseTree tree = parser.source_text(); Console.WriteLine(tree.ToStringTree(parser)); //VhdlAntlrVisitor visitor = new VhdlAntlrVisitor(); //Console.WriteLine(visitor.Visit(tree)); Console.Write("Press any key to continue . . . "); Console.ReadKey(true); }
public void ParseVerilog2001() { var inputStream = new AntlrInputStream(@" module generate_example(); reg read,write = 0; reg [31:0] data_in = 0; reg [3:0] address = 0; wire [31:0] data_out; initial begin $monitor ($time, read, write, address, data_in, data_out); #1 read = 0; // why only for read #3 repeat (16) begin data_in = $random; write = 1; #1 address = address + 1; end write = 0; address = 0; #3 repeat (16) begin read = 1; #1 address = address + 1; end read = 0; #1 $finish; end endmodule "); var lexer = new Verilog2001Lexer(inputStream); var commonTokenStream = new CommonTokenStream(lexer); var parser = new Verilog2001Parser(commonTokenStream); var visitor = new CstBuilderForAntlr4(parser); visitor.Visit(parser.source_text()); Console.WriteLine(visitor.FinishParsing()); }