public bool FrameAdvance(IController controller, bool render, bool renderSound) { _controller = controller; _lagged = true; DriveLightOn = false; CheckSpriteLimit(); PSG.BeginFrame(Cpu.TotalExecutedCycles); Cpu.Debug = Tracer.IsEnabled(); if (SuperGrafx) { VPC.ExecFrame(render); } else { VDC1.ExecFrame(render); } PSG.EndFrame(Cpu.TotalExecutedCycles); if (_lagged) { _lagCount++; _isLag = true; } else { _isLag = false; } Frame++; return(true); }
// The SuperGrafx has 32K of RAM and a different port configuration to allow // I/O access to VDC1, VDC2, and the VPC. byte ReadMemorySGX(int addr) { if (addr < 0xFFFFF) // read ROM return RomData[addr % RomLength]; if (addr >= 0x1F0000 && addr < 0x1F8000) // read RAM return Ram[addr & 0x7FFF]; if (addr >= 0x1FE000) // hardware page. { if (addr < 0x1FE400) { addr &= 0x1F; if (addr <= 0x07) return VDC1.ReadVDC(addr); if (addr <= 0x0F) return VPC.ReadVPC(addr); if (addr <= 0x17) return VDC2.ReadVDC(addr); return 0xFF; } if (addr < 0x1FE800) { Cpu.PendingCycles--; return VCE.ReadVCE(addr); } if (addr < 0x1FEC00) return IOBuffer; if (addr < 0x1FF000) { IOBuffer = (byte)(Cpu.ReadTimerValue() | (IOBuffer & 0x80)); return IOBuffer; } if (addr >= 0x1FF000 && addr < 0x1FF400) { IOBuffer = ReadInput(); return IOBuffer; } if ((addr & ~1) == 0x1FF400) return IOBuffer; if (addr == 0x1FF402) { IOBuffer = Cpu.IRQControlByte; return IOBuffer; } if (addr == 0x1FF403) { IOBuffer = (byte)(Cpu.ReadIrqStatus() | (IOBuffer & 0xF8)); return IOBuffer; } } Log.Error("MEM", "UNHANDLED READ: {0:X6}", addr); return 0xFF; }
void WriteMemorySGX(int addr, byte value) { if (addr >= 0x1F0000 && addr < 0x1F8000) // write RAM. Ram[addr & 0x7FFF] = value; else if (addr >= 0x1FE000) // hardware page. { if (addr < 0x1FE400) { addr &= 0x1F; if (addr <= 0x07) VDC1.WriteVDC(addr, value); else if (addr <= 0x0F) VPC.WriteVPC(addr, value); else if (addr <= 0x17) VDC2.WriteVDC(addr, value); } else if (addr < 0x1FE800) { Cpu.PendingCycles--; VCE.WriteVCE(addr, value); } else if (addr < 0x1FEC00) { IOBuffer = value; PSG.WritePSG((byte)addr, value, Cpu.TotalExecutedCycles); } else if (addr == 0x1FEC00) { IOBuffer = value; Cpu.WriteTimer(value); } else if (addr == 0x1FEC01) { IOBuffer = value; Cpu.WriteTimerEnable(value); } else if (addr >= 0x1FF000 && addr < 0x1FF400) { IOBuffer = value; WriteInput(value); } else if (addr == 0x1FF402) { IOBuffer = value; Cpu.WriteIrqControl(value); } else if (addr == 0x1FF403) { IOBuffer = value; Cpu.WriteIrqStatus(); } else Log.Error("MEM", "unhandled hardware write [{0:X6}] : {1:X2}", addr, value); } else Log.Error("MEM", "UNHANDLED WRITE: {0:X6}:{1:X2}", addr, value); }
public void FrameAdvance(bool render, bool rendersound) { _lagged = true; DriveLightOn = false; Frame++; CheckSpriteLimit(); PSG.BeginFrame(Cpu.TotalExecutedCycles); Cpu.Debug = Tracer.Enabled; if (SuperGrafx) { VPC.ExecFrame(render); } else { VDC1.ExecFrame(render); } PSG.EndFrame(Cpu.TotalExecutedCycles); if (_lagged) { _lagCount++; _isLag = true; } else { _isLag = false; } }
private byte ReadMemoryPopulous(int addr) { if (addr >= 0x80000 && addr < 0x88000) { return(PopulousRAM[addr & 0x7FFF]); } if (addr < 0xFFFFF) // read ROM { return(RomData[addr % RomLength]); } if (addr >= 0x1F0000 && addr < 0x1F8000) // read RAM { return(Ram[addr & 0x1FFF]); } if (addr >= 0x1FE000) // hardware page. { if (addr < 0x1FE400) { return(VDC1.ReadVDC(addr)); } if (addr < 0x1FE800) { Cpu.PendingCycles--; return(VCE.ReadVCE(addr)); } if (addr < 0x1FEC00) { return(IOBuffer); } if (addr < 0x1FF000) { IOBuffer = (byte)(Cpu.ReadTimerValue() | (IOBuffer & 0x80)); return(IOBuffer); } if (addr >= 0x1FF000 && addr < 0x1FF400) { IOBuffer = ReadInput(); return(IOBuffer); } if ((addr & ~1) == 0x1FF400) { return(IOBuffer); } if (addr == 0x1FF402) { IOBuffer = Cpu.IRQControlByte; return(IOBuffer); } if (addr == 0x1FF403) { IOBuffer = (byte)(Cpu.ReadIrqStatus() | (IOBuffer & 0xF8)); return(IOBuffer); } } Log.Error("MEM", "UNHANDLED READ: {0:X6}", addr); return(0xFF); }
byte ReadMemory(int addr) { if (addr < 0xFFFFF) // read ROM { return(RomData[addr % RomLength]); } if (addr >= 0x1F0000 && addr < 0x1F8000) // read RAM { return(Ram[addr & 0x1FFF]); } if (addr >= 0x1FE000) // hardware page. { if (addr < 0x1FE400) { return(VDC1.ReadVDC(addr)); } if (addr < 0x1FE800) { Cpu.PendingCycles--; return(VCE.ReadVCE(addr)); } if (addr < 0x1FEC00) { return(IOBuffer); } if (addr < 0x1FF000) { IOBuffer = (byte)(Cpu.ReadTimerValue() | (IOBuffer & 0x80)); return(IOBuffer); } if (addr >= 0x1FF000 && addr < 0x1FF400) { IOBuffer = ReadInput(); return(IOBuffer); } if ((addr & ~1) == 0x1FF400) { return(IOBuffer); } if (addr == 0x1FF402) { IOBuffer = Cpu.IRQControlByte; return(IOBuffer); } if (addr == 0x1FF403) { IOBuffer = (byte)(Cpu.ReadIrqStatus() | (IOBuffer & 0xF8)); return(IOBuffer); } if (addr >= 0x1FF800) { return(ReadCD(addr)); } } if (addr >= 0x1EE000 && addr <= 0x1EE7FF) // BRAM { if (BramEnabled && BramLocked == false) { return(BRAM[addr & 0x7FF]); } return(0xFF); } //CoreComm.MemoryCallbackSystem.CallRead((uint)addr); Log.Error("MEM", "UNHANDLED READ: {0:X6}", addr); return(0xFF); }
void WriteMemory(int addr, byte value) { if (addr >= 0x1F0000 && addr < 0x1F8000) // write RAM. { Ram[addr & 0x1FFF] = value; } else if (addr >= 0x1FE000) // hardware page. { if (addr < 0x1FE400) { VDC1.WriteVDC(addr, value); } else if (addr < 0x1FE800) { Cpu.PendingCycles--; VCE.WriteVCE(addr, value); } else if (addr < 0x1FEC00) { IOBuffer = value; PSG.WritePSG((byte)addr, value, Cpu.TotalExecutedCycles); } else if (addr == 0x1FEC00) { IOBuffer = value; Cpu.WriteTimer(value); } else if (addr == 0x1FEC01) { IOBuffer = value; Cpu.WriteTimerEnable(value); } else if (addr >= 0x1FF000 && addr < 0x1FF400) { IOBuffer = value; WriteInput(value); } else if (addr == 0x1FF402) { IOBuffer = value; Cpu.WriteIrqControl(value); } else if (addr == 0x1FF403) { IOBuffer = value; Cpu.WriteIrqStatus(); } else if (addr >= 0x1FF800) { WriteCD(addr, value); } else { Log.Error("MEM", "unhandled hardware write [{0:X6}] : {1:X2}", addr, value); } } else if (addr >= 0x1EE000 && addr <= 0x1EE7FF) // BRAM { if (BramEnabled && BramLocked == false) { BRAM[addr & 0x7FF] = value; SaveRamModified = true; } } else { Log.Error("MEM", "UNHANDLED WRITE: {0:X6}:{1:X2}", addr, value); } //CoreComm.MemoryCallbackSystem.CallWrite((uint)addr); }
private void SyncState(Serializer ser) { ser.BeginSection("PCEngine"); Cpu.SyncState(ser); VCE.SyncState(ser); VDC1.SyncState(ser, 1); PSG.SyncState(ser); if (SuperGrafx) { VPC.SyncState(ser); VDC2.SyncState(ser, 2); } if (TurboCD) { ADPCM.SyncState(ser); CDAudio.SyncState(ser); SCSI.SyncState(ser); ser.Sync("CDRAM", ref CDRam, false); if (SuperRam != null) { ser.Sync("SuperRAM", ref SuperRam, false); } if (ArcadeCard) { ArcadeCardSyncState(ser); } } ser.Sync("RAM", ref Ram, false); ser.Sync("IOBuffer", ref IOBuffer); ser.Sync("CdIoPorts", ref CdIoPorts, false); ser.Sync("BramLocked", ref BramLocked); ser.Sync("Frame", ref frame); ser.Sync("Lag", ref _lagCount); ser.Sync("IsLag", ref _isLag); if (Cpu.ReadMemory21 == ReadMemorySF2) { ser.Sync("SF2MapperLatch", ref SF2MapperLatch); } if (PopulousRAM != null) { ser.Sync("PopulousRAM", ref PopulousRAM, false); } if (BRAM != null) { ser.Sync("BRAM", ref BRAM, false); } ser.EndSection(); if (ser.IsReader) { SyncAllByteArrayDomains(); } }
void WriteMemoryCD(int addr, byte value) { if (addr >= 0x1F0000 && addr < 0x1F8000) // write RAM. { Ram[addr & 0x1FFF] = value; } else if (addr >= 0x100000 && addr < 0x110000) // write CD-RAM { CDRam[addr & 0xFFFF] = value; } else if (addr >= 0xD0000 && addr < 0x100000 && SuperRam != null) // Super SysCard RAM { SuperRam[addr - 0xD0000] = value; } else if (addr >= 0x1FE000) // hardware page. { if (addr < 0x1FE400) { VDC1.WriteVDC(addr, value); } else if (addr < 0x1FE800) { Cpu.PendingCycles--; VCE.WriteVCE(addr, value); } else if (addr < 0x1FEC00) { IOBuffer = value; PSG.WritePSG((byte)addr, value, Cpu.TotalExecutedCycles); } else if (addr == 0x1FEC00) { IOBuffer = value; Cpu.WriteTimer(value); } else if (addr == 0x1FEC01) { IOBuffer = value; Cpu.WriteTimerEnable(value); } else if (addr >= 0x1FF000 && addr < 0x1FF400) { IOBuffer = value; WriteInput(value); } else if (addr == 0x1FF402) { IOBuffer = value; Cpu.WriteIrqControl(value); } else if (addr == 0x1FF403) { IOBuffer = value; Cpu.WriteIrqStatus(); } else if (addr >= 0x1FF800) { WriteCD(addr, value); } else { Log.Error("MEM", "unhandled hardware write [{0:X6}] : {1:X2}", addr, value); } } else if (addr >= 0x80000 && addr < 0x88000 && ArcadeCard) // Arcade Card { var page = ArcadePage[(addr >> 13) & 3]; ArcadeRam[page.EffectiveAddress] = value; page.Increment(); } else if (addr >= 0x1EE000 && addr <= 0x1EE7FF) // BRAM { if (BramEnabled && BramLocked == false) { BRAM[addr & 0x7FF] = value; SaveRamModified = true; } } else { Log.Error("MEM", "UNHANDLED WRITE: {0:X6}:{1:X2}", addr, value); } }
byte ReadMemoryCD(int addr) { if (addr < 0x80000) // read ROM { return(RomData[addr % RomLength]); } if (addr >= 0x1F0000 && addr < 0x1F8000) // read RAM { return(Ram[addr & 0x1FFF]); } if (addr >= 0x100000 && addr < 0x110000) // read CD RAM { return(CDRam[addr & 0xFFFF]); } if (addr >= 0xD0000 && addr < 0x100000 && SuperRam != null) // Super SysCard RAM { return(SuperRam[addr - 0xD0000]); } if (addr >= 0x1FE000) // hardware page. { if (addr < 0x1FE400) { return(VDC1.ReadVDC(addr)); } if (addr < 0x1FE800) { Cpu.PendingCycles--; return(VCE.ReadVCE(addr)); } if (addr < 0x1FEC00) { return(IOBuffer); } if (addr < 0x1FF000) { IOBuffer = (byte)(Cpu.ReadTimerValue() | (IOBuffer & 0x80)); return(IOBuffer); } if (addr >= 0x1FF000 && addr < 0x1FF400) { IOBuffer = ReadInput(); return(IOBuffer); } if ((addr & ~1) == 0x1FF400) { return(IOBuffer); } if (addr == 0x1FF402) { IOBuffer = Cpu.IRQControlByte; return(IOBuffer); } if (addr == 0x1FF403) { IOBuffer = (byte)(Cpu.ReadIrqStatus() | (IOBuffer & 0xF8)); return(IOBuffer); } if (addr >= 0x1FF800) { return(ReadCD(addr)); } } if (addr >= 0x80000 && addr < 0x88000 && ArcadeCard) { var page = ArcadePage[(addr >> 13) & 3]; byte value = ArcadeRam[page.EffectiveAddress]; page.Increment(); return(value); } if (addr >= 0x1EE000 && addr <= 0x1EE7FF) // BRAM { if (BramEnabled && BramLocked == false) { return(BRAM[addr & 0x7FF]); } return(0xFF); } Log.Error("MEM", "UNHANDLED READ: {0:X6}", addr); return(0xFF); }
private void WriteMemorySF2(int addr, byte value) { if ((addr & 0x1FFC) == 0x1FF0) { // Set SF2 pager. SF2MapperLatch = (byte)(addr & 0x03); if (SF2UpdateCDLMappings) { CDLMappingApplyRange(Cpu.Mappings, "ROM", 0x40, 0x80000, (SF2MapperLatch + 1) * 0x80000); } return; } if (addr >= 0x1F0000 && addr < 0x1F8000) // write RAM. { Ram[addr & 0x1FFF] = value; } else if (addr >= 0x1FE000) // hardware page. { if (addr < 0x1FE400) { VDC1.WriteVDC(addr, value); } else if (addr < 0x1FE800) { Cpu.PendingCycles--; VCE.WriteVCE(addr, value); } else if (addr < 0x1FEC00) { IOBuffer = value; PSG.WritePSG((byte)addr, value, Cpu.TotalExecutedCycles); } else if (addr == 0x1FEC00) { IOBuffer = value; Cpu.WriteTimer(value); } else if (addr == 0x1FEC01) { IOBuffer = value; Cpu.WriteTimerEnable(value); } else if (addr >= 0x1FF000 && addr < 0x1FF400) { IOBuffer = value; WriteInput(value); } else if (addr == 0x1FF402) { IOBuffer = value; Cpu.WriteIrqControl(value); } else if (addr == 0x1FF403) { IOBuffer = value; Cpu.WriteIrqStatus(); } else { Log.Error("MEM", "unhandled hardware write [{0:X6}] : {1:X2}", addr, value); } } else { Log.Error("MEM", "UNHANDLED WRITE: {0:X6}:{1:X2}", addr, value); } }