public static string GetByType(SMU.Status type)
{
if (!status.TryGetValue(type, out string output))
{
return("Unknown Status");
}
return(output);
}
private bool WaitForPowerTable()
{
if (cpu.powerTable.dramBaseAddress == 0)
{
HandleError("Could not initialize power table.\nClose the application and try again.");
return(false);
}
if (WaitForDriverLoad() && cpu.utils.WinIoStatus == Utils.LibStatus.OK)
{
SMU.Status status = SMU.Status.FAILED;
Stopwatch timer = new Stopwatch();
int timeout = 10000;
cpu.powerTable.ConfiguredClockSpeed = MEMCFG.Frequency;
cpu.powerTable.MemRatio = MEMCFG.Ratio;
timer.Start();
// Refresh each 2 seconds until table is transferred to DRAM or timeout
do
{
status = cpu.RefreshPowerTable();
if (status != SMU.Status.OK)
{
// It's ok to block the current thread
Thread.Sleep(2000);
}
}while (status != SMU.Status.OK && timer.Elapsed.TotalMilliseconds < timeout);
timer.Stop();
if (status != SMU.Status.OK)
{
HandleError("Could not get power table.\nSkipping.");
return(false);
}
return(true);
}
else
{
HandleError("I/O driver is not responding or not loaded.");
return(false);
}
}
private void ReadPowerConfig()
{
if (dramBaseAddress > 0)
{
try
{
SMU.Status status = OPS.TransferTableToDram();
if (status != SMU.Status.OK)
{
status = OPS.TransferTableToDram(); // retry
}
if (status != SMU.Status.OK)
{
return;
}
for (int i = 0; i < table.Length; ++i)
{
InteropMethods.GetPhysLong((UIntPtr)dramBaseAddress + (i * 0x4), out uint data);
table[i] = data;
}
if (table.Any(v => v != 0))
{
PowerTable.ConfiguredClockSpeed = MEMCFG.Frequency;
PowerTable.Table = table;
}
}
catch (EntryPointNotFoundException ex)
{
throw new ApplicationException(ex.Message);
}
catch (DllNotFoundException ex)
{
throw new ApplicationException(ex.Message);
}
}
}
public ulong GetDramBaseAddress()
{
uint[] args = new uint[6];
ulong address = 0;
SMU.Status status = SMU.Status.FAILED;
switch (Smu.SMU_TYPE)
{
// SummitRidge, PinnacleRidge
case SMU.SmuType.TYPE_CPU0:
case SMU.SmuType.TYPE_CPU1:
args[0] = 0;
status = SendSmuCommand(Smu.SMU_MSG_GetDramBaseAddress - 1, ref args);
if (status != SMU.Status.OK)
{
return(0);
}
status = SendSmuCommand(Smu.SMU_MSG_GetDramBaseAddress, ref args);
if (status != SMU.Status.OK)
{
return(0);
}
address = args[0];
args[0] = 0;
status = SendSmuCommand(Smu.SMU_MSG_GetDramBaseAddress + 2, ref args);
if (status != SMU.Status.OK)
{
return(0);
}
break;
// Matisse, CastlePeak, Rome
case SMU.SmuType.TYPE_CPU2:
status = SendSmuCommand(Smu.SMU_MSG_GetDramBaseAddress, ref args);
if (status != SMU.Status.OK)
{
return(0);
}
address = args[0];
break;
// Renoir
case SMU.SmuType.TYPE_APU1:
status = SendSmuCommand(Smu.SMU_MSG_GetDramBaseAddress, ref args);
if (status != SMU.Status.OK)
{
return(0);
}
address = args[0] | ((ulong)args[1] << 32);
break;
// RavenRidge, RavenRidge2, Picasso
case SMU.SmuType.TYPE_APU0:
uint[] parts = new uint[2];
args[0] = 3;
status = SendSmuCommand(Smu.SMU_MSG_GetDramBaseAddress - 1, ref args);
if (status != SMU.Status.OK)
{
return(0);
}
args[0] = 3;
status = SendSmuCommand(Smu.SMU_MSG_GetDramBaseAddress, ref args);
if (status != SMU.Status.OK)
{
return(0);
}
// First base
parts[0] = args[0];
args[0] = 5;
status = SendSmuCommand(Smu.SMU_MSG_GetDramBaseAddress - 1, ref args);
if (status != SMU.Status.OK)
{
return(0);
}
status = SendSmuCommand(Smu.SMU_MSG_GetDramBaseAddress, ref args);
if (status != SMU.Status.OK)
{
return(0);
}
// Second base
parts[1] = args[0];
address = (ulong)parts[1] << 32 | parts[0];
break;
default:
break;
}
if (status == SMU.Status.OK)
{
return(address);
}
return(0);
}
private void ReadPowerConfig()
{
#if DEBUG
/*uint prev1 = 0;
* uint prev2 = 0;
* for (; ; )
* {
* uint cmd1 = 0, cmd2 = 0;
* uint arg1 = 0, arg2 = 0;
* uint rsp1 = 0, rsp2 = 0;
*
* ops.SmuReadReg(0x03B10564, ref arg1);
* ops.SmuReadReg(0x03B10528, ref cmd1);
* ops.SmuReadReg(0x03B10598, ref rsp1);
* if (cmd1 != prev1)
* {
* prev1 = cmd1;
* Console.WriteLine($"1 -> 0x{cmd1:X2}: 0x{arg1:X8}: 0x{rsp1:X8}");
* }
*
* ops.SmuReadReg(ops.Smu.SMU_ADDR_ARG, ref arg2);
* ops.SmuReadReg(ops.Smu.SMU_ADDR_MSG, ref cmd2);
* ops.SmuReadReg(ops.Smu.SMU_ADDR_RSP, ref rsp2);
* if (cmd2 != prev2)
* {
* prev2 = cmd2;
* Console.WriteLine($"2 -> 0x{cmd2:X2}: 0x{arg2:X8}: 0x{rsp2:X8}");
* }
* }*/
#endif
if (dramBaseAddress > 0)
{
try
{
SMU.Status status = OPS.TransferTableToDram();
if (status != SMU.Status.OK)
{
status = OPS.TransferTableToDram(); // retry
}
if (status != SMU.Status.OK)
{
return;
}
for (int i = 0; i < table.Length; ++i)
{
InteropMethods.GetPhysLong((UIntPtr)dramBaseAddress + (i * 0x4), out uint data);
table[i] = data;
}
if (table.Any(v => v != 0))
{
PowerTable.ConfiguredClockSpeed = MEMCFG.Frequency;
PowerTable.Table = table;
}
}
catch (EntryPointNotFoundException ex)
{
throw new ApplicationException(ex.Message);
}
catch (DllNotFoundException ex)
{
throw new ApplicationException(ex.Message);
}
}
}
