/// <summary>
/// Read data from backup register
/// </summary>
public static int ReadRegister(Registers register)
{
int registerData;
Native_BackupRegister_ReadRegister((byte)register, out registerData);
return registerData;
}
public SimpleSimulator()
{
Memory = new Memory();
Registers = new Registers();
Machine = new Machine(Memory, Registers);
Assembler = new Assembler();
}
private static void SetFlags(ref Registers regs, bool Z, bool S, bool HC, bool CA)
{
regs.Z = Z;
regs.S = S;
regs.HC = HC;
regs.CA = CA;
}
public x86CPU(Config cfg)
{
_cfg = cfg;
Registers = new Registers();
State = new CPUState();
Memmory = new Memmory(_cfg);
_opcode = new Opcode();
}
public void SetUp()
{
_memory = new Memory();
_actualOutput = null;
_registers = new Registers();
_registers.ValueWrittenToOutputRegister += (c => _actualOutput += c);
_machine = new Machine(_memory, _registers);
}
public void ThisIndexer_WithProperRegisterIndex_ExpectedEqualsValue(int registerIndex, byte value)
{
// Arrange
var registers = new Registers();
// Act
registers[registerIndex] = value;
// Assert
Assert.AreEqual(value, registers[registerIndex]);
}
private static void RunProgram(string assemblyCode)
{
Assembler assembler = new Assembler();
Instruction[] instructions = assembler.Assemble(assemblyCode);
Memory memory = new Memory();
memory.LoadInstructions(instructions);
Registers registers = new Registers();
registers.ValueWrittenToOutputRegister += System.Console.Write;
Machine machine = new Machine(memory, registers);
machine.Run(25);
System.Console.ReadLine();
}
public void ShouldBeAbleToSaveRegistersState()
{
Registers expectedRegisters = new Registers();
Random random = new Random();
for (byte register = 0; register <= 0x0F; register++)
expectedRegisters[register] = (byte)random.Next(0x00, byte.MaxValue);
StateSaver stateSaver = new StateSaver();
stateSaver.SaveRegisters(expectedRegisters, _registersSaveFile);
FileAssert.Exists(_registersSaveFile);
Registers actualRegisters = stateSaver.LoadRegisters(_registersSaveFile);
for (byte register = 0; register < 0x0F; register++)
Assert.AreEqual(expectedRegisters[register], actualRegisters[register]);
}
internal abstract Registers CopyRegisters(Registers regs);
public void AndValue(Registers register)
{
register.EAX &= register.EAX;
}
protected override byte GetRegisterHighValue()
{
return(Registers.GetPC().GetHi());
}
protected override byte GetRegisterLowValue()
{
return(Registers.GetPC().GetLo());
}
public void Execute(Registers registers)
{
registers.ESI++;
}
/// <summary>Asserts, that the value of the register of the given type is equal to the given value.</summary>
/// <param name="type"></param>
/// <param name="value"></param>
/// <param name="message"></param>
public void AssertRegisterEquals(Registers type, uint value, string message = null)
{
var register = Processor.Registers[type];
Assert.AreEqual(value, register.Value, message ?? $"Register {type} does not have the expected value");
}
public void WriteRegister(Registers r, byte value)
{
switch (r)
{
case Registers.A: proc.rA = value; break;
case Registers.B: proc.rB = value; break;
case Registers.C: proc.rC = value; break;
case Registers.D: proc.rD = value; break;
case Registers.E: proc.rE = value; break;
case Registers.F: proc.rF = value; break;
case Registers.I: proc.rI = value; break;
case Registers.M: proc.rM = value; break;
case Registers.R: proc.rR = value; break;
case Registers.H: proc.rH = value; break;
case Registers.L: proc.rL = value; break;
case Registers.HX: proc.rHX = value; break;
case Registers.HY: proc.rHY = value; break;
case Registers.LX: proc.rLX = value; break;
case Registers.LY: proc.rLY = value; break;
default:
throw new InvalidOperandSizeException(r.ToString() + " is not 8 bit register");
}
}
public void Execute(Registers registers, DataSection dataSection)
{
registers.ESP = registers.EDI;
}
public RegisterToken(int line, int pos, Registers register)
: base(line, pos)
{
this.Register = register;
}
private void WriteReg(Registers reg, byte param)
{
_i2cDevice.Write(new byte[] { (byte)reg, param });
}
private byte ReadByte(Registers reg)
{
_i2cDevice.WriteByte((byte)reg);
return(_i2cDevice.ReadByte());
}
public void XorValue(Registers register)
{
register.EBP ^= register.EDX;
}
void EXX()
{
Registers.ExchangeRegisterSet();
}
public void AndValue(Registers register)
{
register.ECX &= register.ESP;
}
internal StackFrame CreateFrame(Thread thread, FrameType type, TargetMemoryAccess target,
TargetAddress address, TargetAddress stack,
TargetAddress frame_pointer, Registers regs)
{
if ((address.IsNull) || (address.Address == 0))
return null;
Method method = process.SymbolTableManager.Lookup (address);
if (method != null)
return new StackFrame (
thread, type, address, stack, frame_pointer, regs, method);
Symbol name = process.SymbolTableManager.SimpleLookup (address, false);
return new StackFrame (
thread, type, address, stack, frame_pointer, regs,
process.NativeLanguage, name);
}
public ModRmExecutorSegment32b(Registers regs, FlagsRegister flags, byte[] mem, ModRMDecoder modRm) : base(regs,
flags, mem, modRm)
{
}
public void Compare(ref Flags flags, Registers registers)
{
flags.ZeroFlag = registers.EAX == registers.ESI;
}
public void ExecuteId(Registers Id)
{
byte opcode = Fetch();
switch (opcode)
{
case 9: //ADD ID,BC
opAdd16(ComposeRegister(Id), ComposeRegister(Registers.BC));
break;
case 25: //ADD ID,DE
opAdd16(ComposeRegister(Id), ComposeRegister(Registers.DE));
break;
case 41: //ADD ID,ID
opAdd16(ComposeRegister(Id), ComposeRegister(Id));
break;
case 57: //ADD ID,SP
opAdd16(ComposeRegister(Id), ComposeRegister(Registers.SP));
break;
case 33: //LD ID,nn
opLd16(ComposeRegister(Id), FetchImmediateWord());
break;
case 34: //LD (nn),ID
opLd16(ComposeImmediateIndirectWord(), ComposeRegister(Id));
break;
case 42: //LD ID,(nn)
opLd16(ComposeRegister(Id), ComposeImmediateIndirectWord());
break;
case 35: //INC ID
opInc16(ComposeRegister(Id));
break;
case 43: //DEC ID
opDec16(ComposeRegister(Id));
break;
case 36: //INC IDH
opInc8(ComposeRegisterHi(Id));
break;
case 44: //INC IDL
opInc8(ComposeRegisterLo(Id));
break;
case 52: //INC (ID+d)
opInc8(ComposeIndexIndirect(Id));
break;
case 37: //DEC IDH
opDec8(ComposeRegisterHi(Id));
break;
case 45: //DEC IDL
opDec8(ComposeRegisterLo(Id));
break;
case 53: //DEC (ID+d)
opDec8(ComposeIndexIndirect(Id));
break;
case 38: //LD IDH,n
opLd8(ComposeRegisterHi(Id), FetchImmediateByte());
break;
case 46: //LD IDL,n
opLd8(ComposeRegisterLo(Id), FetchImmediateByte());
break;
case 54: //LD (ID+d),n
opLd8(ComposeIndexIndirect(Id), FetchImmediateByte());
break;
case 68: //LD B,IDH
opLd8(ComposeRegister(Registers.B), ComposeRegisterHi(Id));
break;
case 69: //LD B,IDL
opLd8(ComposeRegister(Registers.B), ComposeRegisterLo(Id));
break;
case 70: //LD B,(ID+d)
opLd8(ComposeRegister(Registers.B), ComposeIndexIndirect(Id));
break;
case 76: //LD C,IDH
opLd8(ComposeRegister(Registers.C), ComposeRegisterHi(Id));
break;
case 77: //LD C,IDL
opLd8(ComposeRegister(Registers.C), ComposeRegisterLo(Id));
break;
case 78: //LD C,(ID+d)
opLd8(ComposeRegister(Registers.C), ComposeIndexIndirect(Id));
break;
case 84: //LD D,IDH
opLd8(ComposeRegister(Registers.D), ComposeRegisterHi(Id));
break;
case 85: //LD D,IDL
opLd8(ComposeRegister(Registers.D), ComposeRegisterLo(Id));
break;
case 86: //LD D,(ID+d)
opLd8(ComposeRegister(Registers.D), ComposeIndexIndirect(Id));
break;
case 92: //LD E,IDH
opLd8(ComposeRegister(Registers.E), ComposeRegisterHi(Id));
break;
case 93: //LD E,IDL
opLd8(ComposeRegister(Registers.E), ComposeRegisterLo(Id));
break;
case 94: //LD E,(ID+d)
opLd8(ComposeRegister(Registers.E), ComposeIndexIndirect(Id));
break;
case 96: //LD IDH,B
opLd8(ComposeRegisterHi(Id), ComposeRegister(Registers.B));
break;
case 97: //LD IDH,C
opLd8(ComposeRegisterHi(Id), ComposeRegister(Registers.C));
break;
case 98: //LD IDH,D
opLd8(ComposeRegisterHi(Id), ComposeRegister(Registers.D));
break;
case 99: //LD IDH,E
opLd8(ComposeRegisterHi(Id), ComposeRegister(Registers.E));
break;
case 100: //LD IDH,IDH
//execute_id := 9;
break;
case 101: //LD IDH,IDL
opLd8(ComposeRegisterHi(Id), ComposeRegisterLo(Id));
break;
case 102: //LD H,(ID+d)
opLd8(ComposeRegister(Registers.H), ComposeIndexIndirect(Id));
break;
case 103: //LD IDH,A
opLd8(ComposeRegisterHi(Id), ComposeRegister(Registers.A));
break;
case 104: //LD IDL,B
opLd8(ComposeRegisterLo(Id), ComposeRegister(Registers.B));
break;
case 105: //LD IDL,C
opLd8(ComposeRegisterLo(Id), ComposeRegister(Registers.C));
break;
case 106: //LD IDL,D
opLd8(ComposeRegisterLo(Id), ComposeRegister(Registers.D));
break;
case 107: //LD IDL,E
opLd8(ComposeRegisterLo(Id), ComposeRegister(Registers.E));
break;
case 108: //LD IDL,IDH
opLd8(ComposeRegisterLo(Id), ComposeRegisterHi(Id));
break;
case 109: //LD IDL,IDL
//execute_id := 9;
break;
case 110: //LD L,(ID+d)
opLd8(ComposeRegister(Registers.L), ComposeIndexIndirect(Id));
break;
case 111: //LD IDL,A
opLd8(ComposeRegisterLo(Id), ComposeRegister(Registers.A));
break;
case 112: //LD (ID+d),B
opLd8(ComposeIndexIndirect(Id), ComposeRegister(Registers.B));
break;
case 113: //LD (ID+d),C
opLd8(ComposeIndexIndirect(Id), ComposeRegister(Registers.C));
break;
case 114: //LD (ID+d),D
opLd8(ComposeIndexIndirect(Id), ComposeRegister(Registers.D));
break;
case 115: //LD (ID+d),E
opLd8(ComposeIndexIndirect(Id), ComposeRegister(Registers.E));
break;
case 116: //LD (ID+d),H
opLd8(ComposeIndexIndirect(Id), ComposeRegister(Registers.H));
break;
case 117: //LD (ID+d),L
opLd8(ComposeIndexIndirect(Id), ComposeRegister(Registers.L));
break;
case 119: //LD (ID+d),A
opLd8(ComposeIndexIndirect(Id), ComposeRegister(Registers.A));
break;
case 124: //LD A,IDH
opLd8(ComposeRegister(Registers.A), ComposeRegisterHi(Id));
break;
case 125: //LD A,IDL
opLd8(ComposeRegister(Registers.A), ComposeRegisterLo(Id));
break;
case 126: //LD A,(ID+d)
opLd8(ComposeRegister(Registers.A), ComposeIndexIndirect(Id));
break;
case 132: //ADD A,IDH
opAddA(ComposeRegisterHi(Id));
break;
case 133: //ADD A,IDL
opAddA(ComposeRegisterLo(Id));
break;
case 134: //ADD A,(ID+d)
opAddA(ComposeIndexIndirect(Id));
break;
case 140: //ADC A,IDH
opAdcA(ComposeRegisterHi(Id));
break;
case 141: //ADC A,IDL
opAdcA(ComposeRegisterLo(Id));
break;
case 142: //ADC A,(ID+d)
opAdcA(ComposeIndexIndirect(Id));
break;
case 148: //SUB IDH
opSubA(ComposeRegisterHi(Id));
break;
case 149: //SUB IDL
opSubA(ComposeRegisterLo(Id));
break;
case 150: //SUB (ID+d)
opSubA(ComposeIndexIndirect(Id));
break;
case 156: //SBC A,IDH
opSbcA(ComposeRegisterHi(Id));
break;
case 157: //SBC A,IDL
opSbcA(ComposeRegisterLo(Id));
break;
case 158: //SBC A,(ID+d)
opSbcA(ComposeIndexIndirect(Id));
break;
case 164: //AND IDH
opAddA(ComposeRegisterHi(Id));
break;
case 165: //AND IDL
opAndA(ComposeRegisterLo(Id));
break;
case 166: //AND (ID+d)
opAndA(ComposeIndexIndirect(Id));
break;
case 172: //XOR IDH
opXorA(ComposeRegisterHi(Id));
break;
case 173: //XOR IDL
opXorA(ComposeRegisterLo(Id));
break;
case 174: //XOR (ID+d)
opXorA(ComposeIndexIndirect(Id));
break;
case 180: //OR IDH
opOrA(ComposeRegisterHi(Id));
break;
case 181: //OR IDL
opOrA(ComposeRegisterLo(Id));
break;
case 182: //OR (ID+d)
opOrA(ComposeIndexIndirect(Id));
break;
case 188: //CP IDH
opCpA(ComposeRegisterHi(Id));
break;
case 189: //CP IDL
opCpA(ComposeRegisterLo(Id));
break;
case 190: //CP (ID+d)
opCpA(ComposeIndexIndirect(Id));
break;
case 203: //prefix CB
Operand op1 = ComposeIndexIndirect(Id);
byte op = Fetch();
ExecuteIdCb(op, op1);
break;
case 225: //POP ID
opPop16(ComposeRegister(Id));
break;
case 227: //EX (SP),ID
opEx(ComposeRegisterIndirect(Registers.SP), ComposeRegister(Id));
break;
case 229: //PUSH ID
opPush16(ComposeRegister(Id));
break;
case 233: //JP ID
opJp(ComposeRegister(Id));
break;
case 249: //LD SP,ID
opLd16(ComposeRegister(Registers.SP), ComposeRegister(Id));
break;
default:
throw new InvalidOpcodeException("Execute ID", opcode);
}
}
public ushort Read16BitRegister(Registers r)
{
switch (r)
{
case Registers.BC: return proc.rBC;
case Registers.DE: return proc.rDE;
case Registers.HL: return proc.rHL;
case Registers.IX: return proc.rIX;
case Registers.IY: return proc.rIY;
case Registers.PC: return proc.rPC;
case Registers.SP: return proc.rSP;
case Registers.AF: return proc.rAF;
default:
throw new InvalidOperandSizeException(r.ToString() + " is not 16 bit register");
}
}
private void loadFromStream(Stream stream)
{
if (stream.Length != 49179L && stream.Length != 131103L)
{
PlatformFactory.Platform.ShowWarning("Invalid SNA file size!", "SNA loader");
return;
}
this._spec.CPU.Tact += 1000UL;
this._spec.DoReset();
if (this._spec is ISpectrum128K)
{
((ISpectrum128K)this._spec).Port7FFD = 48;
}
byte[] array = new byte[27];
stream.Read(array, 0, 27);
byte[] array2 = new byte[49152];
stream.Read(array2, 0, 49152);
this._spec.SetRamImage(5, array2, 0, 16384);
this._spec.SetRamImage(2, array2, 16384, 16384);
this._spec.SetRamImage(0, array2, 32768, 16384);
Registers registers = new Registers();
registers.I = array[0];
registers._HL = (ushort)((int)array[1] + 256 * (int)array[2]);
registers._DE = (ushort)((int)array[3] + 256 * (int)array[4]);
registers._BC = (ushort)((int)array[5] + 256 * (int)array[6]);
registers._AF = (ushort)((int)array[7] + 256 * (int)array[8]);
registers.HL = (ushort)((int)array[9] + 256 * (int)array[10]);
registers.DE = (ushort)((int)array[11] + 256 * (int)array[12]);
registers.BC = (ushort)((int)array[13] + 256 * (int)array[14]);
registers.IY = (ushort)((int)array[15] + 256 * (int)array[16]);
registers.IX = (ushort)((int)array[17] + 256 * (int)array[18]);
registers.R = array[20];
registers.AF = (ushort)((int)array[21] + 256 * (int)array[22]);
registers.SP = (ushort)((int)array[23] + 256 * (int)array[24]);
this._spec.CPU.regs = registers;
this._spec.CPU.IM = (byte)((array[25] & 3));
if (this._spec.CPU.IM > 2)
{
this._spec.CPU.IM = 2;
}
this._spec.CPU.IFF2 = ((array[19] & 4) == 4);
this._spec.CPU.IFF1 = this._spec.CPU.IFF2;
this._spec.CPU.HALTED = false;
if (this._spec is ISpectrum)
{
((ISpectrum)this._spec).PortFE = array[26];
}
ushort num = (ushort)this._spec.ReadMemory(this._spec.CPU.regs.SP);
num |= (ushort)(this._spec.ReadMemory((ushort)(this._spec.CPU.regs.SP + 1)) << 8);
if (stream.Length > 49179L)
{
num = (ushort)stream.ReadByte();
num |= (ushort)(stream.ReadByte() << 8);
this._spec.CPU.regs.PC = num;
byte b = (byte)stream.ReadByte();
if (this._spec is ISpectrum128K)
{
((ISpectrum128K)this._spec).Port7FFD = b;
}
stream.ReadByte();
if ((b & 7) != 0)
{
this._spec.SetRamImage((int)(b & 7), this._spec.GetRamImage(0), 0, 16384);
}
for (int i = 0; i < 8; i++)
{
if (i != 5 && i != 2 && i != (int)(b & 7))
{
stream.Read(array2, 0, 16384);
this._spec.SetRamImage(i, array2, 0, 16384);
}
}
return;
}
Registers regs = this._spec.CPU.regs;
regs.SP += 1;
Registers regs2 = this._spec.CPU.regs;
regs2.SP += 1;
this._spec.CPU.regs.PC = num;
}
public string PrettyPrint(Registers registers)
{
StringBuilder str = new StringBuilder ();
str.AppendFormat ("#{0} insn, signal {1}\n", InstructionCount, Signal);
str.Append ("{\n");
str.AppendFormat (" Register changes:\n");
foreach (RegisterChange regChange in RegisterChanges) {
str.AppendFormat (" ${0} (#{1}): 0x{2:X} ({3})\n", registers.FindRegisterByNum (regChange.Regnum).Name, regChange.Regnum,
ByteHelper.ByteArrayToUInt64 (regChange.Value, 0, (int)registers.FindRegisterByNum (regChange.Regnum).Size),
ByteHelper.ByteArrayToHexString (regChange.Value));
}
str.AppendFormat (" Memory changes:\n");
foreach (MemoryChange memchange in MemoryChanges) {
str.AppendFormat (" 0x{0:X}: {1}\n", memchange.Address, ByteHelper.ByteArrayToHexString (memchange.Value));
}
str.Append ("}\n");
return str.ToString ();
}
public void Execute(Registers registers, Sections.DataSection dataSection)
{
if (dataSection.Variables.ContainsKey(ModifiyValue.Address))
{
Type type = dataSection.Variables[ModifiyValue.Address].GetType();
if (type == typeof(byte))
{
dataSection.Variables[ModifiyValue.Address].Value = Convert.ToByte(registers.ECX);
}
else if (type == typeof(short))
{
dataSection.Variables[ModifiyValue.Address].Value = Convert.ToInt16(registers.ECX);
}
else if (type == typeof(ushort))
{
dataSection.Variables[ModifiyValue.Address].Value = Convert.ToUInt16(registers.ECX);
}
else if (type == typeof(int))
{
dataSection.Variables[ModifiyValue.Address].Value = Convert.ToInt32(registers.ECX);
}
else if (type == typeof(uint))
{
dataSection.Variables[ModifiyValue.Address].Value = Convert.ToUInt32(registers.ECX);
}
else if (type == typeof(long))
{
dataSection.Variables[ModifiyValue.Address].Value = Convert.ToInt64(registers.ECX);
}
else if (type == typeof(ulong))
{
dataSection.Variables[ModifiyValue.Address].Value = Convert.ToUInt64(registers.ECX);
}
else if (type == typeof(IntPtr))
{
dataSection.Variables[ModifiyValue.Address].Value = new IntPtr(registers.ECX);
}
else if (type == typeof(UIntPtr))
{
dataSection.Variables[ModifiyValue.Address].Value = new UIntPtr(Convert.ToUInt32(registers.ECX));
}
else
{
throw new Exception("Variable type \"" + type + "\" not supported at " + ToString());
}
return;
}
try
{
unsafe
{
switch (ModifiyValue.Size)
{
case 4:
{
*(int *)(ModifiyValue.Address) = registers.ECX;
break;
}
//x64
/*case 8:
* {
* registers.RCX = *(long*)(ModifiyAddress.Address);
* break;
* }*/
default:
{
throw new NotSupportedException(ToString());
}
}
}
} catch { throw new Exception("\"" + ToString() + "\"Invalid memory address"); }
}
public void XorValue(Registers register)
{
register.EDX ^= register.ESI;
}
public string PrintRegisters(Registers registers)
{
return String.Format (
"RAX={0} RBX={1} RCX={2} RDX={3}\n" +
"RSI={4} RDI={5} RBP={6} RSP={7}\n" +
"R8 ={8} R9 ={9} R10={10} R11={11}\n" +
"R12={12} R13={13} R14={14} R15={15}\n" +
"RIP={16} EFLAGS={17}\n",
format (registers [(int) X86_Register.RAX]),
format (registers [(int) X86_Register.RBX]),
format (registers [(int) X86_Register.RCX]),
format (registers [(int) X86_Register.RDX]),
format (registers [(int) X86_Register.RSI]),
format (registers [(int) X86_Register.RDI]),
format (registers [(int) X86_Register.RBP]),
format (registers [(int) X86_Register.RSP]),
format (registers [(int) X86_Register.R8]),
format (registers [(int) X86_Register.R9]),
format (registers [(int) X86_Register.R10]),
format (registers [(int) X86_Register.R11]),
format (registers [(int) X86_Register.R12]),
format (registers [(int) X86_Register.R13]),
format (registers [(int) X86_Register.R14]),
format (registers [(int) X86_Register.R15]),
format (registers [(int) X86_Register.RIP]),
PrintRegister (registers [(int) X86_Register.EFLAGS]));
}
public void Handle(Application.Boundaries.Register.Output output)
{
Registers.Add(output);
}
internal override StackFrame CreateFrame(Thread thread, FrameType type, TargetMemoryAccess memory, Registers regs)
{
TargetAddress address = new TargetAddress (
memory.AddressDomain, regs [(int) X86_Register.RIP].GetValue ());
TargetAddress stack_pointer = new TargetAddress (
memory.AddressDomain, regs [(int) X86_Register.RSP].GetValue ());
TargetAddress frame_pointer = new TargetAddress (
memory.AddressDomain, regs [(int) X86_Register.RBP].GetValue ());
return CreateFrame (thread, type, memory, address, stack_pointer, frame_pointer, regs);
}
void SetRegisters(Registers regs, TargetMemoryAccess target,
Architecture arch, Column[] columns)
{
long cfa_addr = GetRegisterValue (regs, 1, columns [0]);
TargetAddress cfa = new TargetAddress (
target.AddressDomain, cfa_addr);
for (int i = 1; i < columns.Length; i++) {
GetValue (target, regs, cfa, i+2, columns [i]);
}
}
public void Multiply(Registers registers)
{
registers.EDX *= registers.ESP;
}
public void SetUp()
{
_memory = new Memory();
_registers = new Registers();
_machine = new Machine(_memory, _registers);
}
/// <summary>
/// Returns the value contained in a register
/// et +
/// </summary>
/// <param name="RegisterNumber">The register number</param>
/// <returns></returns>
private byte GetRegister(Registers RegisterNumber)
{
// Buffer d'écriture
byte[] outBuffer = new byte[] { (byte)RegisterNumber };
I2CDevice.I2CWriteTransaction writeTransaction = I2CDevice.CreateWriteTransaction(outBuffer);
// Buffer de lecture
byte[] inBuffer = new byte[1];
I2CDevice.I2CReadTransaction readTransaction = I2CDevice.CreateReadTransaction(inBuffer);
// Tableau des transactions
I2CDevice.I2CTransaction[] transactions = new I2CDevice.I2CTransaction[] { writeTransaction, readTransaction };
// Exécution des transactions
busI2C = new I2CDevice(ConfigSRF08); // Connexion virtuelle du SRF08 au bus I2C
if (busI2C.Execute(transactions, TRANSACTIONEXECUTETIMEOUT) != 0)
{
// Success
//Debug.Print("Received the first data from at device " + busI2C.Config.Address + ": " + ((int)inBuffer[0]).ToString());
}
else
{
// Failed
//Debug.Print("Failed to execute transaction at device: " + busI2C.Config.Address + ".");
}
busI2C.Dispose(); // Déconnexion virtuelle de l'objet Lcd du bus I2C
return inBuffer[0];
}
internal abstract StackFrame CreateFrame(Thread thread, FrameType type, TargetMemoryAccess target, Registers regs);
public void Setup(string errorlog, string destination, Registers targetRegisters, IRegisterTypeResolver registerTypeResolver, params IDataAnalyzer[] analyzers)
{
_errorlog = errorlog;
_destination = destination;
_analyzers = analyzers;
_targetRegisters = targetRegisters;
_registerTypeResolver = registerTypeResolver;
_doc = new XmlDocument ();
_doc.AppendChild (_doc.CreateElement ("Errorlog"));
foreach (IDataAnalyzer analyzer in analyzers)
{
analyzer.Path = _destination;
analyzer.Setup (_doc.DocumentElement);
}
// It is supposed that there exists at least a single file for each prefix.
// Find the highest prefix here
foreach (string file in Directory.GetFiles (_destination))
{
string[] splitted = Path.GetFileName(file).Split ('.');
if (splitted.Length > 0)
{
int prefix;
if (int.TryParse (splitted[0], out prefix) && _highestPrefix < prefix)
_highestPrefix = prefix;
}
}
}
public void SetUp()
{
pc = 0x00000000;
reg = new Registers();
mem = new MemoryMapper(8);
}
public abstract Expression AsExpression(Registers registers);
internal override Registers CopyRegisters(Registers old_regs)
{
Registers regs = new Registers (old_regs);
// According to the AMD64 ABI, rbp, rbx and r12-r15 are preserved
// across function calls.
regs [(int) X86_Register.RBX].Valid = true;
regs [(int) X86_Register.RBP].Valid = true;
regs [(int) X86_Register.R12].Valid = true;
regs [(int) X86_Register.R13].Valid = true;
regs [(int) X86_Register.R14].Valid = true;
regs [(int) X86_Register.R15].Valid = true;
return regs;
}
public override void Execute(ref uint pc, MemoryMapper mem, Registers reg)
{
reg[D] = reg[S] ^ reg[T];
pc += 4;
}
internal override StackFrame GetLMF(ThreadServant thread, TargetMemoryAccess memory, ref TargetAddress lmf_address)
{
TargetAddress lmf = lmf_address;
TargetBinaryReader reader = memory.ReadMemory (lmf_address, 88).GetReader ();
lmf_address = reader.ReadTargetAddress (); // prev
reader.ReadTargetAddress ();
reader.ReadTargetAddress (); // method
TargetAddress rip = reader.ReadTargetAddress ();
if (lmf_address.IsNull)
return null;
TargetAddress rbx = reader.ReadTargetAddress ();
TargetAddress rbp = reader.ReadTargetAddress ();
TargetAddress rsp = reader.ReadTargetAddress ();
TargetAddress r12 = reader.ReadTargetAddress ();
TargetAddress r13 = reader.ReadTargetAddress ();
TargetAddress r14 = reader.ReadTargetAddress ();
TargetAddress r15 = reader.ReadTargetAddress ();
Registers regs = new Registers (this);
if ((lmf_address.Address & 1) == 0) {
rip = memory.ReadAddress (rsp - 8);
regs [(int) X86_Register.RIP].SetValue (rsp - 8, rip);
regs [(int) X86_Register.RBP].SetValue (lmf + 40, rbp);
} else {
TargetAddress new_rbp = memory.ReadAddress (rbp);
regs [(int) X86_Register.RIP].SetValue (lmf + 24, rip);
regs [(int) X86_Register.RBP].SetValue (rbp, new_rbp);
rbp = new_rbp;
lmf_address--;
}
regs [(int) X86_Register.RBX].SetValue (lmf + 32, rbx);
regs [(int) X86_Register.RSP].SetValue (lmf + 48, rsp);
regs [(int) X86_Register.R12].SetValue (lmf + 56, r12);
regs [(int) X86_Register.R13].SetValue (lmf + 64, r13);
regs [(int) X86_Register.R14].SetValue (lmf + 72, r14);
regs [(int) X86_Register.R15].SetValue (lmf + 80, r15);
return CreateFrame (thread.Client, FrameType.LMF, memory, rip, rsp, rbp, regs);
}
public override Expression AsExpression(Registers r) => new BinaryExpression("or", _left.AsExpression(r), _right.AsExpression(r), Precedence.OR, Associativity.NONE);
public static StackValue BuildRegister(Registers reg)
{
StackValue value = new StackValue();
value.optype = AddressType.Register;
value.opdata = (int)reg;
return value;
}
public InstructionExecutionTests()
{
_memory = new Memory();
_registers = new Registers();
_machine = new Machine(_memory, _registers);
}
public Register(Registers type, uint value)
{
this.Type = type;
this.Value = value;
}
public void AndValue(Registers register)
{
register.EDI &= register.ESI;
}
public Registers GetRegisters()
{
Registers registers = new Registers ();
ManualResetEvent evt = new ManualResetEvent (false);
MaintPrintRawRegistersCmd printRegistersCmd = new MaintPrintRawRegistersCmd (this,
delegate(string name, uint num, uint size)
{
registers.Add (new Register (num, name, size));
});
printRegistersCmd.CommandFinishedEvent += delegate(GDBCommand obj) {
evt.Set ();
};
QueueCommand (printRegistersCmd);
evt.WaitOne ();
return registers;
}
public void AndValue(Registers register)
{
register.EBX &= register.EDX;
}
/// <summary>Sets the register to the given value.</summary> /// <param name="type"></param> /// <param name="value"></param> public void SetRegister(Registers type, uint value) => Processor.Execute(session => session.SetRegister(type, value));
public override Registers Execute(Registers registersIn) => registersIn.SetWithValue(OutputRegisterC, registersIn[InputA] * registersIn[InputB]);
public byte Read8BitRegister(Registers r)
{
switch (r)
{
case Registers.A: return proc.rA;
case Registers.B: return proc.rB;
case Registers.C: return proc.rC;
case Registers.D: return proc.rD;
case Registers.E: return proc.rE;
case Registers.F: return proc.rF;
case Registers.I: return proc.rI;
case Registers.M: return proc.rM;
case Registers.R: return proc.rR;
case Registers.H: return proc.rH;
case Registers.L: return proc.rL;
case Registers.HX: return proc.rHX;
case Registers.HY: return proc.rHY;
case Registers.LX: return proc.rLX;
case Registers.LY: return proc.rLY;
default:
throw new InvalidOperandSizeException(r.ToString() + " is not 8 bit register");
}
}
/// <returns>Instruction executed successfully</returns> public abstract bool Execute(Registers regs, Stack stack, ref int index);
public void WriteRegister(Registers r, ushort value)
{
switch (r)
{
case Registers.BC: proc.rBC = value; break;
case Registers.DE: proc.rDE = value; break;
case Registers.HL: proc.rHL = value; break;
case Registers.IX: proc.rIX = value; break;
case Registers.IY: proc.rIY = value; break;
case Registers.PC: proc.rPC = value; break;
case Registers.SP: proc.rSP = value; break;
case Registers.AF: proc.rAF = value; break;
default:
throw new InvalidOperandSizeException(r.ToString() + " is not 16 bit register");
}
}
public override void Execute(ref uint pc, MemoryMapper mem, Registers reg)
{
reg[31] = pc + 4;
pc = (pc & 0xF0000000) | (Target << 2);
}
public void SetUp()
{
_registers = new Registers();
}
public AddTests()
{
registers = new Registers();
alu = new Alu(registers);
}
