public void LogicRAMModuleTest() { var sim = new RTLSimulator <LogicRAMModule, LogicRAMModuleInputs>(); sim.ClockCycle(new LogicRAMModuleInputs() { Value = 0xFF }); Assert.AreEqual(0x3F, sim.TopLevel.Avg); sim.ClockCycle(new LogicRAMModuleInputs() { Value = 0xFF }); Assert.AreEqual(0x7F, sim.TopLevel.Avg); sim.ClockCycle(new LogicRAMModuleInputs() { Value = 0xFF }); Assert.AreEqual(0xBF, sim.TopLevel.Avg); sim.ClockCycle(new LogicRAMModuleInputs() { Value = 0xFF }); Assert.AreEqual(0xFF, sim.TopLevel.Avg); }
public void IntDividerPipelineModuleTest() { var t = new RTLSimulator <IntDividerPipelineModule, IntDividerPipelineModuleInputs>(); var tl = t.TopLevel; var rnd = new Random(Environment.TickCount); var testCases = new List <IntDividerPipelineModuleTestRecord>(); var testResults = new List <IntDividerPipelineModuleTestResult>(); int max = 1000; foreach (var i in Enumerable.Range(0, max)) { var testCase = new IntDividerPipelineModuleTestRecord(rnd.Next(), rnd.Next()); testCases.Add(testCase); t.ClockCycle(new IntDividerPipelineModuleInputs() { inReady = true, inNumerator = testCase.Numerator, inDenominator = testCase.Denominator }); if (tl.OutReady) { testResults.Add(new IntDividerPipelineModuleTestResult(tl.OutRes, tl.OutRem)); } } while (tl.OutReady) { t.ClockCycle(new IntDividerPipelineModuleInputs()); if (tl.OutReady) { testResults.Add(new IntDividerPipelineModuleTestResult(tl.OutRes, tl.OutRem)); } } Assert.AreEqual(max, testResults.Count); foreach (var i in Enumerable.Range(0, max)) { var testCase = testCases[i]; var testResult = testResults[i]; Assert.AreEqual(testCase.Result, testResult.Result, $"res failed for {testCase.Numerator} / {testCase.Denominator}"); Assert.AreEqual(testCase.Remainder, testResult.Remainder, $"rem failed for {testCase.Numerator} / {testCase.Denominator}"); } }
public void ReadTest() { var sim = new RTLSimulator <TModule, RegistersModuleInput>(); var tl = sim.TopLevel; foreach (var idx in IncRange) { sim.ClockCycle(new RegistersModuleInput() { RD = idx, WE = true, WriteData = idx }); } sim.ClockCycle(new RegistersModuleInput() { Read = true, RS1Addr = 1, RS2Addr = 2 }); sim.ClockCycle(new RegistersModuleInput() { Read = true, RS1Addr = 1, RS2Addr = 2 }); sim.ClockCycle(new RegistersModuleInput() { Read = true, RS1Addr = 1, RS2Addr = 2 }); foreach (var rs1 in IncRange) { foreach (var rs2 in IncRange) { do { sim.ClockCycle(new RegistersModuleInput() { Read = true, RS1Addr = rs1, RS2Addr = rs2 }); }while (!tl.Ready); Assert.AreEqual(rs1, tl.RS1); Assert.AreEqual(rs2, tl.RS2); } } }
public void StallControlPipelineModuleTest_StallPrev() { var t = new RTLSimulator <StallControlPipelineModule, StallControlInputs>(); t.TraceToVCD(VCDOutputPath()); Action <StallControlOutput> assert = (expected) => Assert.IsTrue(DeepDiff.DeepEquals(expected, t.TopLevel.outResult)); t.ClockCycle(new StallControlInputs() { inProcessed = true, inData = 3, inReady = true }); assert(new StallControlOutput()); t.ClockCycle(new StallControlInputs { inProcessed = true }); assert(new StallControlOutput() { result = 1, stage0Stalled = true }); t.ClockCycle(new StallControlInputs { inProcessed = true }); assert(new StallControlOutput() { result = 5, stage0Stalled = true }); t.ClockCycle(new StallControlInputs { inProcessed = true }); assert(new StallControlOutput() { result = 9, stage0Stalled = true }); t.ClockCycle(new StallControlInputs { inProcessed = true, inReady = true }); assert(new StallControlOutput() { result = 13 }); t.ClockCycle(new StallControlInputs { inProcessed = true, inReady = true }); assert(new StallControlOutput() { result = 17, ready = true }); t.ClockCycle(new StallControlInputs { inProcessed = true }); }
static void Main(string[] args) { Console.WriteLine($"Quokka.FPGA version: {typeof(QuokkaRunner).Assembly.GetName().Version}"); Console.WriteLine($"Quokka.RTL version: {typeof(RTLBitArray).Assembly.GetName().Version}"); Ctor(); var c = new C() { v = true }; var sw = new Stopwatch(); sw.Start(); var sim = new RTLSimulator <VGAModule, VGAModuleInputs>(); var tl = sim.TopLevel; //sim.TraceToVCD(VCDOutputPath()); var b = new RTLBitArray(100000).Unsigned(); for (int i = 0; i < 80000; i++) { if (b < i) { throw new Exception(); } } var lapsed = sw.ElapsedMilliseconds; sw.Restart(); int vSyncCounter = 0, hSyncCounter = 0; for (int row = 0; row < 100 /*525*/; row++) { for (int col = 0; col < 800; col++) { sim.ClockCycle(new VGAModuleInputs()); if (!tl.VSync) { vSyncCounter++; } if (!tl.HSync) { hSyncCounter++; } } } Console.WriteLine($"Done in {sw.ElapsedMilliseconds} ms"); }
public void LogicRAMIndexingModuleTest() { var sim = new RTLSimulator <LogicRAMIndexingModule, LogicRAMIndexingModuleInputs>(true); sim.TraceToVCD(VCDOutputPath()); var tl = sim.TopLevel; sim.ClockCycle(new LogicRAMIndexingModuleInputs() { WE = true, WriteAddr = 0, WriteData = 0x66 }); sim.ClockCycle(new LogicRAMIndexingModuleInputs() { WE = true, WriteAddr = 1, WriteData = 0xAA }); sim.ClockCycle(new LogicRAMIndexingModuleInputs() { WE = true, WriteAddr = 2, WriteData = 0x55 }); sim.ClockCycle(new LogicRAMIndexingModuleInputs() { WE = true, WriteAddr = 3, WriteData = 0xFF }); sim.ClockCycle(new LogicRAMIndexingModuleInputs() { ReadAddr = 2, OpData = 0xF0 }); Assert.AreEqual(false, tl.CmpMemLhs); Assert.AreEqual(true, tl.CmpMemRhs); Assert.AreEqual(0xF5, tl.LogicMemLhs); Assert.AreEqual(0x50, tl.LogicMemRhs); Assert.AreEqual(0x65, tl.MathMemLhs); Assert.AreEqual(0x45, tl.MathMemRhs); Assert.AreEqual(0xFF, tl.MemLhsRhs); sim.ClockCycle(new LogicRAMIndexingModuleInputs() { ReadAddr = 0, OpData = 0x50 }); Assert.AreEqual(true, tl.CmpMemLhs); Assert.AreEqual(false, tl.CmpMemRhs); Assert.AreEqual(0x76, tl.LogicMemLhs); Assert.AreEqual(0x40, tl.LogicMemRhs); Assert.AreEqual(0x16, tl.MathMemLhs); Assert.AreEqual(0xB6, tl.MathMemRhs); Assert.AreEqual(0x10, tl.MemLhsRhs); var tb = sim.TBAdapter(RTLVerilogConfig); tb.PostSynthTimingSimulation(); }
public void VGAModule_FrameTest() { var sim = new RTLSimulator <VGAModule, VGAModuleInputs>(true); /* * // VCD output takes about 15 minutes to write * sim.TraceToVCD( * VCDOutputPath(), * new RTLModuleSnapshotConfig() * { * Include = RTLModuleSnapshotConfigInclude.Inputs | RTLModuleSnapshotConfigInclude.Outputs, * MaxNestingLevel = 0 * }); */ var tl = sim.TopLevel; int pixelCounter = 0; for (int row = 0; row < 628; row++) { for (int col = 0; col < 1 /*056*/; col++) { if (tl.IsVisible) { pixelCounter++; } sim.ClockCycle(new VGAModuleInputs()); } } //Assert.AreEqual(800 * 600, pixelCounter); var tb = sim.TBAdapter(RTLVerilogConfig); //tb.TranslateModule(); //tb.SaveTestbench(); tb.PostSynthTimingSimulation(); //Assert.AreEqual(480, hSyncCounter, "HSync is wrong"); //Assert.AreEqual(640, hSyncCounter, "VSync is wrong"); }
public void FillTest() { var sim = new RTLSimulator <TModule, RegistersModuleInput>(); var tl = sim.TopLevel; foreach (var idx in IncRange) { sim.ClockCycle(new RegistersModuleInput() { RD = idx, WE = true, WriteData = idx + 1 }); if (idx == 0) { Assert.AreEqual(0U, tl.State.x[0]); } else { Assert.AreEqual((uint)(idx + 1), tl.State.x[idx]); } } }
public void StallControlTestPipelineModuleTest() { var sim = new RTLSimulator <StallControlTestPipelineModule, StallControlTestPipelineModuleInputs>(); sim.TraceToVCD(VCDOutputPath()); var dataLog = new IntegrationTestDataLogger(); // initial values dataLog.setInputs(new StallControlTestPipelineModuleInputs()); Action <StallControlTestPipelineModuleInputs> clockCycle = (inputs) => { dataLog.currentClock++; dataLog.setInputs(inputs); sim.ClockCycle(inputs); }; Action <byte[]> assertStateCounters = (values) => { var pl = sim.TopLevel.PipelineProps.Single().GetValue(sim.TopLevel) as IRTLPipeline; var head = pl.Diag.Head; var s0 = head.Peek <StallControlTestPipelineStage0>(); var s1 = head.Peek <StallControlTestPipelineStage1>(); var s2 = head.Peek <StallControlTestPipelineStage2>(); var s3 = head.Peek <StallControlTestPipelineStage3>(); Assert.AreEqual(values[0], s0.State.stage0Counter); Assert.AreEqual(values[1], s1.State.stage1Counter); Assert.AreEqual(values[2], s2.State.stage2Counter); Assert.AreEqual(values[3], s3.State.stage3Counter); }; Action <StallControlTestOutput> assert = (expected) => { var compare = DeepDiff.DeepCompare(expected, sim.TopLevel.outResult); if (compare != null) { Assert.Fail($"{string.Join(".", compare.Path.Select(p => p.Name))}: Expecting {compare.lhs}, Actual {compare.rhs}. {compare.Messages.ToCSV()}"); } dataLog.SetOutputs(expected); }; var idle = new StallControlTestPipelineModuleInputs(); clockCycle(idle); assert(new StallControlTestOutput() { stage3Counter = 1 }); clockCycle(idle); assert(new StallControlTestOutput() { stage2Counter = 1, stage3Counter = 2 }); clockCycle(idle); assert(new StallControlTestOutput() { stage1Counter = 1, stage2Counter = 2, stage3Counter = 3 }); clockCycle(idle); assert(new StallControlTestOutput() { stage0Counter = 1, stage1Counter = 2, stage2Counter = 3, stage3Counter = 4 }); // all counters should be at 4 assertStateCounters(new byte[] { 4, 4, 4, 4 }); #region stage3 stall control // stall stage3 clockCycle(new StallControlTestPipelineModuleInputs() { stallStage3 = true }); assertStateCounters(new byte[] { 4, 4, 4, 4 }); assert(new StallControlTestOutput() { stage0Counter = 1, stage1Counter = 2, stage2Counter = 3, stage3Counter = 4, pipelineStalled = true, stage0Stalled = true, stage1Stalled = true, stage2Stalled = true, stage3Stalled = true }); // stall pipeline from stage 3 clockCycle(new StallControlTestPipelineModuleInputs() { stallPipeline = true, stallStage3 = true }); assertStateCounters(new byte[] { 4, 4, 4, 4 }); assert(new StallControlTestOutput() { stage0Counter = 1, stage1Counter = 2, stage2Counter = 3, stage3Counter = 4, pipelineStalled = true, stage0Stalled = true, stage1Stalled = true, stage2Stalled = true, stage3Stalled = true }); // stall stage2 from stage 3 clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage3 = true }); assertStateCounters(new byte[] { 4, 4, 4, 5 }); assert(new StallControlTestOutput() { stage0Counter = 2, stage1Counter = 3, stage2Counter = 4, stage3Counter = 5, pipelineStalled = false, stage0Stalled = true, stage1Stalled = true, stage2Stalled = true, stage3Stalled = false }); // stall stage 2 from stage 3 again clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage3 = true }); assertStateCounters(new byte[] { 4, 4, 4, 6 }); assert(new StallControlTestOutput() { stage0Counter = 2, stage1Counter = 3, stage2Counter = 4, stage3Counter = 6, pipelineStalled = false, stage0Stalled = true, stage1Stalled = true, stage2Stalled = true, stage3Stalled = false }); #endregion #region stage2 stall control // stall stage2 clockCycle(new StallControlTestPipelineModuleInputs() { stallStage2 = true }); assertStateCounters(new byte[] { 4, 4, 4, 7 }); assert(new StallControlTestOutput() { stage0Counter = 2, stage1Counter = 3, stage2Counter = 4, stage3Counter = 7, pipelineStalled = false, stage0Stalled = true, stage1Stalled = true, stage2Stalled = true, stage3Stalled = false }); // stall pipeline from stage 2 clockCycle(new StallControlTestPipelineModuleInputs() { stallPipeline = true, stallStage2 = true }); assertStateCounters(new byte[] { 4, 4, 4, 7 }); assert(new StallControlTestOutput() { stage0Counter = 2, stage1Counter = 3, stage2Counter = 4, stage3Counter = 7, pipelineStalled = true, stage0Stalled = true, stage1Stalled = true, stage2Stalled = true, stage3Stalled = true }); // stall stage1 from stage 2 clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage2 = true }); assertStateCounters(new byte[] { 4, 4, 5, 8 }); assert(new StallControlTestOutput() { stage0Counter = 2, stage1Counter = 3, stage2Counter = 4, stage3Counter = 8, pipelineStalled = false, stage0Stalled = true, stage1Stalled = true, stage2Stalled = false, stage3Stalled = false }); // stall stage1 from stage 2 again clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage2 = true }); assertStateCounters(new byte[] { 4, 4, 6, 9 }); assert(new StallControlTestOutput() { stage0Counter = 3, stage1Counter = 4, stage2Counter = 5, stage3Counter = 9, pipelineStalled = false, stage0Stalled = true, stage1Stalled = true, stage2Stalled = false, stage3Stalled = false }); // stall stage1 from stage 2 one more time clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage2 = true }); assertStateCounters(new byte[] { 4, 4, 7, 10 }); assert(new StallControlTestOutput() { stage0Counter = 3, stage1Counter = 4, stage2Counter = 6, stage3Counter = 10, pipelineStalled = false, stage0Stalled = true, stage1Stalled = true, stage2Stalled = false, stage3Stalled = false }); #endregion stage2 stall control #region stage1 stall control clockCycle(new StallControlTestPipelineModuleInputs() { stallStage1 = true }); assertStateCounters(new byte[] { 4, 4, 8, 11 }); assert(new StallControlTestOutput() { stage0Counter = 3, stage1Counter = 4, stage2Counter = 7, stage3Counter = 11, pipelineStalled = false, stage0Stalled = true, stage1Stalled = true, stage2Stalled = false, stage3Stalled = false }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPipeline = true, stallStage1 = true }); assertStateCounters(new byte[] { 4, 4, 8, 11 }); assert(new StallControlTestOutput() { stage0Counter = 3, stage1Counter = 4, stage2Counter = 7, stage3Counter = 11, pipelineStalled = true, stage0Stalled = true, stage1Stalled = true, stage2Stalled = true, stage3Stalled = true }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage1 = true }); assertStateCounters(new byte[] { 4, 5, 9, 12 }); assert(new StallControlTestOutput() { stage0Counter = 3, stage1Counter = 4, stage2Counter = 8, stage3Counter = 12, pipelineStalled = false, stage0Stalled = true, stage1Stalled = false, stage2Stalled = false, stage3Stalled = false }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage1 = true }); assertStateCounters(new byte[] { 4, 6, 10, 13 }); assert(new StallControlTestOutput() { stage0Counter = 3, stage1Counter = 4, stage2Counter = 9, stage3Counter = 13, pipelineStalled = false, stage0Stalled = true, stage1Stalled = false, stage2Stalled = false, stage3Stalled = false }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage1 = true }); assertStateCounters(new byte[] { 4, 7, 11, 14 }); assert(new StallControlTestOutput() { stage0Counter = 4, stage1Counter = 5, stage2Counter = 10, stage3Counter = 14, pipelineStalled = false, stage0Stalled = true, stage1Stalled = false, stage2Stalled = false, stage3Stalled = false }); #endregion stage1 stall control #region stage2 stall control clockCycle(new StallControlTestPipelineModuleInputs() { stallStage0 = true }); assertStateCounters(new byte[] { 4, 8, 12, 15 }); assert(new StallControlTestOutput() { stage0Counter = 4, stage1Counter = 6, stage2Counter = 11, stage3Counter = 15, pipelineStalled = false, stage0Stalled = true, stage1Stalled = false, stage2Stalled = false, stage3Stalled = false }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPipeline = true, stallStage0 = true }); assertStateCounters(new byte[] { 4, 8, 12, 15 }); assert(new StallControlTestOutput() { stage0Counter = 4, stage1Counter = 6, stage2Counter = 11, stage3Counter = 15, pipelineStalled = true, stage0Stalled = true, stage1Stalled = true, stage2Stalled = true, stage3Stalled = true }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage0 = true }); assertStateCounters(new byte[] { 5, 9, 13, 16 }); assert(new StallControlTestOutput() { stage0Counter = 4, stage1Counter = 7, stage2Counter = 12, stage3Counter = 16, pipelineStalled = false, stage0Stalled = false, stage1Stalled = false, stage2Stalled = false, stage3Stalled = false }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage0 = true }); assertStateCounters(new byte[] { 6, 10, 14, 17 }); assert(new StallControlTestOutput() { stage0Counter = 4, stage1Counter = 8, stage2Counter = 13, stage3Counter = 17, pipelineStalled = false, stage0Stalled = false, stage1Stalled = false, stage2Stalled = false, stage3Stalled = false }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage0 = true }); assertStateCounters(new byte[] { 7, 11, 15, 18 }); assert(new StallControlTestOutput() { stage0Counter = 4, stage1Counter = 9, stage2Counter = 14, stage3Counter = 18, pipelineStalled = false, stage0Stalled = false, stage1Stalled = false, stage2Stalled = false, stage3Stalled = false }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPrev = true, stallStage0 = true }); assertStateCounters(new byte[] { 8, 12, 16, 19 }); assert(new StallControlTestOutput() { stage0Counter = 5, stage1Counter = 10, stage2Counter = 15, stage3Counter = 19, pipelineStalled = false, stage0Stalled = false, stage1Stalled = false, stage2Stalled = false, stage3Stalled = false }); #endregion stage2 stall control // filler in VCD clockCycle(new StallControlTestPipelineModuleInputs() { stallPipeline = true, stallStage3 = true }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPipeline = true, stallStage3 = true }); clockCycle(new StallControlTestPipelineModuleInputs() { stallPipeline = true, stallStage3 = true }); dataLog.Generate(); }