public VIC1541Motherboard(Region initRegion, byte[] initRom)
{
cpu = new MOS6502X();
pla = new VIC1541PLA();
ram = new byte[0x800];
rom = initRom;
serPort = new SerialPort();
via0 = new MOS6522();
via1 = new MOS6522();
cpu.DummyReadMemory = pla.Read;
cpu.ReadMemory = pla.Read;
cpu.WriteMemory = pla.Write;
pla.PeekRam = ((int addr) => { return(ram[addr & 0x07FF]); });
pla.PeekRom = ((int addr) => { return(rom[addr & 0x3FFF]); });
pla.PeekVia0 = via0.Peek;
pla.PeekVia1 = via1.Peek;
pla.PokeRam = ((int addr, byte val) => { ram[addr & 0x07FF] = val; });
pla.PokeRom = ((int addr, byte val) => { });
pla.PokeVia0 = via0.Poke;
pla.PokeVia1 = via1.Poke;
pla.ReadRam = ((ushort addr) => { return(ram[addr & 0x07FF]); });
pla.ReadRom = ((ushort addr) => { return(rom[addr & 0x3FFF]); });
pla.ReadVia0 = via0.Read;
pla.ReadVia1 = via1.Read;
pla.WriteRam = ((ushort addr, byte val) => { ram[addr & 0x07FF] = val; });
pla.WriteRom = ((ushort addr, byte val) => { });
pla.WriteVia0 = via0.Write;
pla.WriteVia1 = via1.Write;
via0CA0 = false;
via0CA1 = false;
via0CB0 = false;
via0CB1 = false;
via0DirA = 0x00;
via0DirB = 0x00;
via0DataA = 0xFF;
via0DataB = 0xFF;
via1CA0 = false;
via1CA1 = false;
via1CB0 = false;
via1CB1 = false;
via1DirA = 0x00;
via1DirB = 0x00;
via1DataA = 0xFF;
via1DataB = 0xFF;
via0.ReadCA0 = (() => { return(via0CA0); });
via0.ReadCA1 = (() => { return(via0CA1); });
via0.ReadCB0 = (() => { return(via0CB0); });
via0.ReadCB1 = (() => { return(via0CB1); });
via0.ReadDirA = (() => { return(via0DirA); });
via0.ReadDirB = (() => { return(via0DirB); });
via0.ReadPortA = (() => { return(via0DataA); });
via0.ReadPortB = (() => { return(via0DataB); });
via0.WriteCA0 = ((bool val) => { via0CA0 = val; });
via0.WriteCA1 = ((bool val) => { via0CA1 = val; });
via0.WriteCB0 = ((bool val) => { via0CB0 = val; });
via0.WriteCB1 = ((bool val) => { via0CB1 = val; });
via0.WriteDirA = ((byte val) => { via0DirA = val; });
via0.WriteDirB = ((byte val) => { via0DirB = val; });
via0.WritePortA = ((byte val) => {
via0DataA = Port.CPUWrite(via0DataA, val, via0DirA);
});
via0.WritePortB = ((byte val) => {
via0DataB = Port.CPUWrite(via0DataB, val, via0DirB);
serPort.DeviceWriteAtn((via0DataB & 0x80) != 0);
serPort.DeviceWriteClock((via0DataB & 0x08) != 0);
serPort.DeviceWriteData((via0DataB & 0x02) != 0);
});
via1.ReadCA0 = (() => { return(via1CA0); });
via1.ReadCA1 = (() => { return(via1CA1); });
via1.ReadCB0 = (() => { return(via1CB0); });
via1.ReadCB1 = (() => { return(via1CB1); });
via1.ReadDirA = (() => { return(via1DirA); });
via1.ReadDirB = (() => { return(via1DirB); });
via1.ReadPortA = (() => { return(via1DataA); });
via1.ReadPortB = (() => { return(via1DataB); });
via1.WriteCA0 = ((bool val) => { via1CA0 = val; });
via1.WriteCA1 = ((bool val) => { via1CA1 = val; });
via1.WriteCB0 = ((bool val) => { via1CB0 = val; });
via1.WriteCB1 = ((bool val) => { via1CB1 = val; });
via1.WriteDirA = ((byte val) => { via1DirA = val; });
via1.WriteDirB = ((byte val) => { via1DirB = val; });
via1.WritePortA = ((byte val) => {
via1DataA = Port.CPUWrite(via1DataA, val, via1DirA);
});
via1.WritePortB = ((byte val) => {
via1DataB = Port.CPUWrite(via1DataB, val, via1DirB);
});
}