void Test(ModbusModel model, ModbusMaster master)
{
master.WriteCoil(1, 2, true);
Assert.AreEqual(true, master.ReadCoil(1, 2));
master.WriteCoil(1, 3, false);
Assert.AreEqual(false, master.ReadCoil(1, 3));
master.WriteCoils(1, 4, bo(false, true));
Assert.AreEqual(bo(true, false, false, true), master.ReadCoils(1, 2, 4));
model.setDIs(11, 12, bo(true, true, false, false));
Assert.AreEqual(true, master.ReadInput(11, 12));
Assert.AreEqual(true, master.ReadInput(11, 13));
Assert.AreEqual(false, master.ReadInput(11, 14));
Assert.AreEqual(false, master.ReadInput(11, 15));
Assert.AreEqual(bo(true, true, false, false), master.ReadInputs(11, 12, 4));
master.WriteRegister(1, 2, 0xabcd);
Assert.AreEqual(0xabcd, master.ReadHoldingRegister(1, 2));
master.WriteRegister(1, 3, 0xcdab);
Assert.AreEqual(0xcdab, master.ReadHoldingRegister(1, 3));
master.WriteRegisters(1, 4, us(0xcda1, 0xcda2));
Assert.AreEqual(us(0xabcd, 0xcdab, 0xcda1, 0xcda2), master.ReadHoldingRegisters(1, 2, 4));
model.setWIs(11, 12, us(0xabcd, 0xcdab, 0xcda1, 0xcda2));
Assert.AreEqual(0xabcd, master.ReadInputRegister(11, 12));
Assert.AreEqual(0xcdab, master.ReadInputRegister(11, 13));
Assert.AreEqual(0xcda1, master.ReadInputRegister(11, 14));
Assert.AreEqual(0xcda2, master.ReadInputRegister(11, 15));
Assert.AreEqual(us(0xabcd, 0xcdab, 0xcda1, 0xcda2), master.ReadInputRegisters(11, 12, 4));
}
//Opto22 32-bit IEEE float. Data is in Big Endian format
private void SetAnalog(ModbusMaster master, int point, float value)
{
var bytes = FloatToByteArray(value);
master.WriteRegister(1, (ushort)(2 * point + 0), (ushort)(bytes[0] << 8 | bytes[1]));
master.WriteRegister(1, (ushort)(2 * point + 1), (ushort)(bytes[2] << 8 | bytes[3]));
}
public static void SharedSlaveTest(ModbusModel model, ModbusMaster master)
{
master.WriteCoil(1, 2, true);
Assert.AreEqual(true, master.ReadCoil(1, 2));
master.WriteCoil(1, 3, false);
Assert.AreEqual(false, master.ReadCoil(1, 3));
master.WriteCoils(1, 4, H.bo(false, true));
Assert.AreEqual(H.bo(true, false, false, true), master.ReadCoils(1, 2, 4));
//race condition avoided by access order
model.setDIs(11, 12, H.bo(true, true, false, false));
Assert.AreEqual(true, master.ReadInput(11, 12));
Assert.AreEqual(true, master.ReadInput(11, 13));
Assert.AreEqual(false, master.ReadInput(11, 14));
Assert.AreEqual(false, master.ReadInput(11, 15));
Assert.AreEqual(H.bo(true, true, false, false), master.ReadInputs(11, 12, 4));
master.WriteRegister(1, 2, 0xabcd);
Assert.AreEqual(0xabcd, master.ReadHoldingRegister(1, 2));
master.WriteRegister(1, 3, 0xcdab);
Assert.AreEqual(0xcdab, master.ReadHoldingRegister(1, 3));
master.WriteRegisters(1, 4, H.us(0xcda1, 0xcda2));
Assert.AreEqual(H.us(0xabcd, 0xcdab, 0xcda1, 0xcda2), master.ReadHoldingRegisters(1, 2, 4));
//race condition avoided by access order
model.setWIs(11, 12, H.us(0xabcd, 0xcdab, 0xcda1, 0xcda2));
Assert.AreEqual(0xabcd, master.ReadInputRegister(11, 12));
Assert.AreEqual(0xcdab, master.ReadInputRegister(11, 13));
Assert.AreEqual(0xcda1, master.ReadInputRegister(11, 14));
Assert.AreEqual(0xcda2, master.ReadInputRegister(11, 15));
Assert.AreEqual(H.us(0xabcd, 0xcdab, 0xcda1, 0xcda2), master.ReadInputRegisters(11, 12, 4));
}
