public static void MipsInterface_RegWrite(MipsInterfaceMemory mi, Int32 address, UInt32 value, UInt32 mask)
{
var reg = (mi_registers)address;
switch (reg)
{
default: break;
case mi_registers.MI_INIT_MODE_REG:
{
if (MipsInterface_UpdateInitMode(mi, value & mask))
{
MipsInterface_ClearRcpInterrupt(mi, MI_INTR_DP);
}
break;
}
case mi_registers.MI_INTR_MASK_REG:
{
MipsInterface_UpdateInterruptMask(mi, value & mask);
CheckInterrupt();
UpdateCount();
if (NextInterrupt < CP0_COUNT_REG)
{
GenInterrupt();
}
break;
}
}
}
public static void MipsInterface_RaiseRcpException(MipsInterfaceMemory mi, UInt32 intr)
{
mi.IntrReg.DataToSlave |= intr;
if ((mi.IntrReg.DataToSlave & mi.IntrMaskReg.DataToSlave) == mi.IntrMaskReg.DataToSlave)
{
RaiseMaskableInterrupt(0x400);
}
}
public static Boolean MipsInterface_UpdateInitMode(MipsInterfaceMemory mi, UInt32 write)
{
Boolean clearDp = false;
/* Set Init Length */
mi.InitModeReg.DataShared &= ~0x7FU;
mi.InitModeReg.DataShared |= write & 0x7F;
/* Clear / Set Init Mode */
if ((write & 0x80U) != 0)
{
mi.InitModeReg.DataToMaster &= ~0x80U;
}
if ((write & 0x100U) != 0)
{
mi.InitModeReg.DataToMaster |= 0x80;
}
/* Clear / Set EBus Test Mode */
if ((write & 0x200) != 0)
{
mi.InitModeReg.DataToMaster &= ~0x100U;
}
if ((write & 0x400) != 0)
{
mi.InitModeReg.DataToMaster |= 0x100;
}
/* Clear DP Intrrupt */
if ((write & 0x800) != 0)
{
mi.InitModeReg.ClearDPInterrupt = clearDp = true;
}
/* Clear / Set RDRAM Reg Mode */
if ((write & 0x1000) != 0)
{
mi.InitModeReg.DataToMaster &= ~0x200U;
}
if ((write & 0x2000) != 0)
{
mi.InitModeReg.DataToMaster |= 0x200;
}
return(clearDp);
}
public void Initialize()
{
CheckDispose();
m_SectionMap = new MemorySection[0x10000];
m_RDRam = new MemorySection(0x100000, 0x00000000);
m_PifMemory = new MemorySection(0x800, 0x1FC00000);
m_PIMem = new ParallelInterfaceMemory();
m_RspMemory = new MemorySection(0x2000, 0x04000000);
m_RspRegisterMemory = new RspRegisterMemory();
m_MiIntefaceMemory = new MipsInterfaceMemory();
if (m_CartMemory != null)
{
AddStream(m_CartMemory);
}
/* Setup the region hashtable */
AddStream(m_RDRam);
AddStream(m_PIMem);
AddStream(m_RspMemory);
AddStream(m_RspRegisterMemory);
AddStream(m_PifMemory);
}
public static void MipsInterface_ClearRcpInterrupt(MipsInterfaceMemory mi, UInt32 intr)
{
mi.IntrReg.DataToSlave &= ~intr;
CheckInterrupt();
}
public static void MipsInterface_SignalRcpInterrupt(MipsInterfaceMemory mi, UInt32 intr)
{
mi.IntrReg.DataToSlave |= intr;
CheckInterrupt();
}
public static void MipsInterface_UpdateInterruptMask(MipsInterfaceMemory mi, UInt32 write)
{
/* Clear / Set SP Mask */
if ((write & 0x1) != 0)
{
mi.IntrMaskReg.DataToMaster &= ~0x1U;
}
if ((write & 0x2) != 0)
{
mi.IntrMaskReg.DataToMaster |= 0x1;
}
/* Clear / Set SI Mask */
if ((write & 0x4) != 0)
{
mi.IntrMaskReg.DataToMaster &= ~0x2U;
}
if ((write & 0x8) != 0)
{
mi.IntrMaskReg.DataToMaster |= 0x2;
}
/* Clear / Set AI Mask */
if ((write & 0x10) != 0)
{
mi.IntrMaskReg.DataToMaster &= ~0x4U;
}
if ((write & 0x20) != 0)
{
mi.IntrMaskReg.DataToMaster |= 0x4;
}
/* Clear / Set VI Mask */
if ((write & 0x40) != 0)
{
mi.IntrMaskReg.DataToMaster &= ~0x8U;
}
if ((write & 0x80) != 0)
{
mi.IntrMaskReg.DataToMaster |= 0x8;
}
/* Clear / Set PI Mask */
if ((write & 0x100) != 0)
{
mi.IntrMaskReg.DataToMaster &= ~0x10U;
}
if ((write & 0x200) != 0)
{
mi.IntrMaskReg.DataToMaster |= 0x10;
}
/* Clear / Set DP Mask */
if ((write & 0x400) != 0)
{
mi.IntrMaskReg.DataToMaster &= ~0x20U;
}
if ((write & 0x800) != 0)
{
mi.IntrMaskReg.DataToMaster |= 0x20;
}
}
