public void RunTest() { hart.Init(0x100); te.LoadTest1(hart); hart.Start(); // The test is passed if we are able to retrieve a dump of the register. // The opcode are tests individually var data = hart.GetRegisterStates(); Assert.IsNotNull(data); }
private void ReadRv(HartConfiguration config, IHart hart) { var rvParser = new RvParser(); var program = rvParser.Parse(config.Source); Console.WriteLine("\n## Program details:\n"); // The program counter starts at 0 ulong programCounter = Convert.ToUInt64(config.RvLoadOffset); hart.Init(programCounter); var opcodes = program.GetOpcodes(); Console.WriteLine(program.GetOpcodeLines()); hart.Load(programCounter, opcodes); }
private void ReadOpcode(HartConfiguration config, IHart hart) { var lowLwevelParser = new Parser(); var myProgram = lowLwevelParser.Parse(config.Source); Console.WriteLine("\n## Program details:\n"); Console.WriteLine(myProgram.GetHumanReadableContent()); // // Init the RISC V hart and start the simulation // hart.Init(myProgram.InitialProgramCounter); // Load each modules to the memory foreach (var subRoutineMarker in myProgram.GetSubRoutineMarker()) { var data = myProgram.GetSubRoutine(subRoutineMarker); hart.Load(subRoutineMarker, data); } }