private void DrawRAMTile(Tile ramTile, Graphics graphicsObj, bool addIncrementForSelectedTiles, bool addIncrementForUserSelectedTiles)
{
int x = -1;
int y = -1;
switch (FPGA.FPGA.Instance.Family)
{
case FPGATypes.FPGAFamily.Artix7:
case FPGATypes.FPGAFamily.Kintex7:
case FPGATypes.FPGAFamily.Virtex7:
case FPGATypes.FPGAFamily.Zynq:
{
if (FPGATypes.IsOrientedMatch(ramTile.Location, IdentifierManager.RegexTypes.BRAM_left))
{
// ram tile are in the bottom middle
x = ramTile.TileKey.X;
y = ramTile.TileKey.Y - (m_ramBlockHeight - 1);
}
else //if (Regex.IsMatch(ramTile.Location, "_R_"))
{
// ram tile are in the bottom middle
x = ramTile.TileKey.X - (m_ramBlockWidth - 1);
y = ramTile.TileKey.Y - (m_ramBlockHeight - 1);
}
break;
}
default:
{
// ram tile are in the bottom right
x = ramTile.TileKey.X - (m_ramBlockWidth - 1);
y = ramTile.TileKey.Y - (m_ramBlockHeight - 1);
break;
}
}
if (FPGA.FPGA.Instance.Contains(x, y))
{
Tile upperLeft = FPGA.FPGA.Instance.GetTile(x, y);
int upperLeftX = upperLeft.TileKey.X * m_view.TileSize;
int upperLeftY = upperLeft.TileKey.Y * m_view.TileSize;
Rectangle rect = new Rectangle();
rect.X = upperLeftX - 1;
rect.Y = upperLeftY - 1;
rect.Width = (m_ramBlockWidth * (m_view.TileSize - 1) + m_ramBlockWidth - 1) - 2;
rect.Height = (m_ramBlockHeight * (m_view.TileSize - 1) + m_ramBlockHeight) - 2;
m_sb.Color = m_view.GetColor(ramTile, addIncrementForSelectedTiles, addIncrementForUserSelectedTiles);
graphicsObj.FillRectangle(m_sb, rect);
}
}
private void DrawNonRAMTile(Tile tile, Graphics graphicsObj, bool addIncrementForSelectedTiles, bool addIncrementForUserSelectedTiles)
{
int upperLeftX = 0;
int upperLeftY = 0;
int widthScale = 1;
int heightScale = 1;
if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(tile);
switch (FPGA.FPGA.Instance.Family)
{
case FPGATypes.FPGAFamily.Artix7:
case FPGATypes.FPGAFamily.Kintex7:
case FPGATypes.FPGAFamily.Virtex7:
case FPGATypes.FPGAFamily.Zynq:
{
if (FPGATypes.IsOrientedMatch(tile.Location, IdentifierManager.RegexTypes.CLB_left))
{
// CLBLL_L_X INT_L_X
upperLeftX = tile.TileKey.X * m_view.TileSize;
upperLeftY = tile.TileKey.Y * m_view.TileSize;
widthScale = 2;
}
else
{
upperLeftX = intTile.TileKey.X * m_view.TileSize;
upperLeftY = intTile.TileKey.Y * m_view.TileSize;
// double size of the rectangle
widthScale = 2;
}
break;
}
case FPGATypes.FPGAFamily.UltraScale:
{
widthScale = FPGATypes.GetCLTile(intTile).Count() + 1;
if (FPGATypes.IsOrientedMatch(tile.Location, IdentifierManager.RegexTypes.CLB_left))
{
// CLBLL_L_X INT_L_X
upperLeftX = tile.TileKey.X * m_view.TileSize;
upperLeftY = tile.TileKey.Y * m_view.TileSize;
}
else
{
upperLeftX = (intTile.TileKey.X - (widthScale == 2 ? 0 : 1)) * m_view.TileSize;
upperLeftY = intTile.TileKey.Y * m_view.TileSize;
// double size of the rectangle
}
break;
}
default:
{
upperLeftX = intTile.TileKey.X * m_view.TileSize;
upperLeftY = intTile.TileKey.Y * m_view.TileSize;
// double size of the rectangle
widthScale = 2;
break;
}
}
}
else if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.Interconnect))
{
// interconnect tiles for CLB have no tiles
return;
}
else
{
upperLeftX = tile.TileKey.X * m_view.TileSize;
upperLeftY = tile.TileKey.Y * m_view.TileSize;
}
m_rect.X = upperLeftX - 1;
m_rect.Y = upperLeftY - 1;
m_rect.Width = (widthScale * (m_view.TileSize - 1) + widthScale) - 2;
m_rect.Height = (heightScale * (m_view.TileSize - 1) + heightScale) - 2;
// default color maybde overwritten
m_sb.Color = m_view.GetColor(tile, addIncrementForSelectedTiles, addIncrementForUserSelectedTiles);
graphicsObj.FillRectangle(m_sb, m_rect);
}