public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { uint clockCounter = 0; Diag.ClockCounter(clockCounter); Sequential handler = () => { FPU.FPUScopeNoSync(); const int width = 10; const int baud = 115200; ComplexFloat[] source = new ComplexFloat[GeneratorTools.ArrayLength(width)]; ComplexFloat[] target = new ComplexFloat[GeneratorTools.ArrayLength(width)]; FPGA.Config.NoSync(source); while (true) { RTX.ReadData(baud, RXD, source); uint start = clockCounter; FFT.Transform(width, source, target, Direction.Forward); uint end = clockCounter; RTX.WriteData(baud, TXD, target, end - start); } }; FPGA.Config.OnStartup(handler); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { const int baud = 115200; uint clockCounter = 0; Diag.ClockCounter(clockCounter); bool internalTXD = true; FPGA.Config.Link(internalTXD, TXD); float op1, op2, res = 0; Sequential handler = () => { FPU.FPUScope(); while (true) { uint start = 0, end = 0; res = 0; var testOp = UART.Read(baud, RXD); UART.ReadFloat(baud, RXD, out op1); UART.ReadFloat(baud, RXD, out op2); switch ((FPUTimingType)testOp) { case FPUTimingType.Add: start = clockCounter; res = op1 + op2; end = clockCounter; break; case FPUTimingType.Sub: start = clockCounter; res = op1 - op2; end = clockCounter; break; case FPUTimingType.Mul: start = clockCounter; res = op1 * op2; end = clockCounter; break; case FPUTimingType.Div: start = clockCounter; res = op1 / op2; end = clockCounter; break; default: start = clockCounter; end = clockCounter; break; } UART.RegisteredWriteFloat(baud, res, out internalTXD); UART.RegisteredWriteUnsigned32(baud, end - start, out internalTXD); } }; FPGA.Config.OnStartup(handler); }