private void Inst_Ldc1(MipsInstruction inst) { if (!CheckCop1Usable()) { CauseException = ExceptionCode.CopUnstable; return; } if (!CheckEvenOddAllowed(inst.Ft)) { CauseFPUException(FPUExceptionType.Unimplemented); return; } Int64 address = ComputeAddress(inst); UInt64 value = DataManipulator.LoadDoublewordUnsigned(address); if (MipsState.CP0Regs.StatusReg.AdditionalFPR) { MipsState.Fpr.WriteFPRUnsigned(inst.Ft, value); } else { MipsState.Fpr.WriteFPR32Unsigned(inst.Ft + 1, (UInt32)(value >> 32)); MipsState.Fpr.WriteFPR32Unsigned(inst.Ft, (UInt32)(value & 0xFFFFFFFF)); } }
private void Inst_Ldr(MipsInstruction inst) { if (MipsState.Operating64BitMode) { /* Thanks to PJ64 Implementation */ Int64 address = ComputeAddress(inst); Int32 offset = (Int32)(address & 7); UInt64 value = DataManipulator.LoadDoublewordUnsigned(address & ~7); MipsState.WriteGPRUnsigned(inst.Rt, MipsState.ReadGPRUnsigned(inst.Rt) & LDRMask[offset]); MipsState.WriteGPRUnsigned(inst.Rt, MipsState.ReadGPRUnsigned(inst.Rt) + (value >> LDRShift[offset])); } else { CauseException = ExceptionCode.ReservedInstruction; } }
private void Inst_Sdr(MipsInstruction inst) { if (MipsState.Operating64BitMode) { /* Thanks to PJ64 implementation */ Int64 address = ComputeAddress(inst); Int32 offset = (Int32)(address & 7); UInt64 value = DataManipulator.LoadDoublewordUnsigned(address & ~7); value &= SDRMask[offset]; value += MipsState.ReadGPRUnsigned(inst.Rt) << SDLShift[offset]; DataManipulator.Store(address & ~7, value); } else { CauseException = ExceptionCode.ReservedInstruction; } }
private void Inst_Ld(MipsInstruction inst) { if (!MipsState.Operating64BitMode) { CauseException = ExceptionCode.ReservedInstruction; } else { Int64 address = ComputeAddress(inst); if ((address & 3) != 0) { CauseException = ExceptionCode.AddressErrorLoad; } else { MipsState.WriteGPRUnsigned(inst.Rt, DataManipulator.LoadDoublewordUnsigned(address)); } } }