public ShiftOperand(MachineOperand op, Opcode opcode, MachineOperand shAmt)
: base(op.Width)
{
this.Operand = op;
this.Opcode = opcode;
this.Shift = shAmt;
}
private void Write(MachineOperand op, MachineInstructionWriter writer)
{
var reg = op as RegisterOperand;
if (reg != null)
{
writer.Write("%{0}", reg.Register.Name);
return;
}
var imm = op as ImmediateOperand;
if (imm != null)
{
writer.Write(imm.Value.ToString());
return;
}
var mem = op as MemoryOperand;
if (mem != null)
{
mem.Write(false, writer);
return;
}
var idx = op as IndexedMemoryOperand;
if (idx != null)
{
idx.Write(false, writer);
return;
}
writer.Write(op.ToString());
}
public ArmMemoryOperand(PrimitiveType width, RegisterStorage regBase, MachineOperand offset) : base(width)
{
if (width == null)
throw new ArgumentNullException("width");
Base = regBase;
Offset = offset;
}
public void Write(MachineOperand op, MachineInstructionWriter writer)
{
var imm = op as ImmediateOperand;
if (imm != null)
{
writer.Write("#");
int imm8 = imm.Value.ToInt32();
if (imm8 > 256 && ((imm8 & (imm8 - 1)) == 0))
{
/* only one bit set, and that later than bit 8.
* Represent as 1<<... .
*/
writer.Write("1<<");
{
uint n = 0;
while ((imm8 & 15) == 0)
{
n += 4; imm8 = imm8 >> 4;
}
// Now imm8 is 1, 2, 4 or 8.
n += (uint)((0x30002010 >> (int)(4 * (imm8 - 1))) & 15);
writer.Write(n);
}
}
else
{
var fmt = (-9 <= imm8 && imm8 <= 9) ? "{0}{1}" : "&{0}{1:X}";
var sign = "";
if (((int)imm8) < 0 && ((int)imm8) > -100)
{
imm8 = -imm8;
sign = "-";
}
writer.Write(fmt,sign,imm8);
}
return;
}
var adr = op as AddressOperand;
if (adr != null)
{
adr.Write(false, writer);
return;
}
var mem = op as ArmMemoryOperand;
if (mem != null)
{
mem.Write(false, writer);
return;
}
var sh = op as ShiftOperand;
if (sh != null)
{
sh.Write(false, writer);
return;
}
if (op == null)
writer.Write("<null>");
else
op.Write(false, writer);
}
public PowerPcInstruction(Opcode opcode, MachineOperand op1, MachineOperand op2, MachineOperand op3, bool setsCR0)
{
this.opcode = opcode;
this.op1 = op1;
this.op2 = op2;
this.op3 = op3;
this.setsCR0 = setsCR0;
}
private void OpToString(MachineOperand op, MachineInstructionWriter writer)
{
if (op is ImmediateOperand)
{
writer.Write("#" + op.ToString());
}
else
{
writer.Write(op.ToString());
}
}
private Identifier GetFpuRegPair(MachineOperand op)
{
var freg0 = ((RegisterOperand)op).Register;
Debug.Assert(freg0.Number % 2 == 0);
var freg1 = Registers.fpuRegs[1 + (freg0.Number & 0x1F)];
var seq = frame.EnsureSequence(
freg0,
freg1,
PrimitiveType.Real64);
return seq;
}
public Address OperandAsCodeAddress(MachineOperand op)
{
AddressOperand ado = op as AddressOperand;
if (ado != null)
return ado.Address;
ImmediateOperand imm = op as ImmediateOperand;
if (imm != null)
{
return orw.ImmediateAsAddress(instrCur.Address, imm);
}
return null;
}
public void EmitBinOp(BinaryOperator binOp, MachineOperand dst, DataType dtDst, Expression left, Expression right, CopyFlags flags)
{
Constant c = right as Constant;
if (c != null)
{
if (c.DataType == PrimitiveType.Byte && left.DataType != c.DataType)
{
right = emitter.Const(left.DataType, c.ToInt32());
}
}
//EmitCopy(dst, new BinaryExpression(binOp, dtDst, left, right), true, emitCc);
EmitCopy(dst, new BinaryExpression(binOp, dtDst, left, right), flags);
}
public IntelInstruction(Opcode code, PrimitiveType dataWidth, PrimitiveType addrWidth, params MachineOperand [] ops)
{
this.code = code;
this.dataWidth = dataWidth;
this.addrWidth = addrWidth;
if (ops.Length >= 1)
{
op1 = ops[0];
if (ops.Length >= 2)
{
op2 = ops[1];
if (ops.Length == 3)
op3 = ops[2];
else if (ops.Length >= 4)
throw new ArgumentException("Too many operands.");
}
}
}
public Expression Transform(IntelInstruction instr, MachineOperand op, PrimitiveType opWidth, X86State state)
{
var reg = op as RegisterOperand;
if (reg != null)
return AluRegister(reg);
var mem = op as MemoryOperand;
if (mem != null)
return CreateMemoryAccess(instr, mem, opWidth, state);
var imm = op as ImmediateOperand;
if (imm != null)
return CreateConstant(imm, opWidth);
var fpu = op as FpuOperand;
if (fpu != null)
return FpuRegister(fpu.StNumber, state);
var addr = op as AddressOperand;
if (addr != null)
return addr.Address;
throw new NotImplementedException(string.Format("Operand {0}", op));
}
private int CompareOperands(MachineOperand opA, MachineOperand opB)
{
if (!opA.GetType().IsAssignableFrom(opB.GetType()))
return -1;
RegisterOperand regOpA = opA as RegisterOperand;
if (regOpA != null)
{
RegisterOperand regOpB = (RegisterOperand) opB;
return (int) regOpB.Register.Number - (int) regOpA.Register.Number;
}
ImmediateOperand immOpA = opA as ImmediateOperand;
if (immOpA != null)
{
ImmediateOperand immOpB = (ImmediateOperand) opB;
return 0; // disregard immediate values.
}
throw new NotImplementedException("NYI");
}
public bool CompareOperands(MachineOperand opA, MachineOperand opB)
{
if (opA.GetType() != opB.GetType())
return false;
RegisterOperand regOpA = opA as RegisterOperand;
if (regOpA != null)
{
RegisterOperand regOpB = (RegisterOperand) opB;
return NormalizeRegisters || regOpA.Register == regOpB.Register;
}
ImmediateOperand immOpA = opA as ImmediateOperand;
if (immOpA != null)
{
var immOpB = (ImmediateOperand) opB;
return NormalizeConstants || immOpA.Value.Equals(immOpB.Value); // disregard immediate values.
}
var addrOpA = opA as AddressOperand;
if (addrOpA != null)
{
var addrOpB = (AddressOperand)opB;
return NormalizeConstants || addrOpA.Address == addrOpB.Address;
}
var memOpA = opA as MemoryOperand;
if (memOpA != null)
{
var memOpB = (MemoryOperand)opB;
if (!base.CompareRegisters(memOpA.Base, memOpB.Base))
return false;
if (!base.CompareRegisters(memOpA.Index, memOpB.Index))
return false;
if (memOpA.Scale != memOpB.Scale)
return false;
return base.CompareValues(memOpA.Offset, memOpB.Offset);
}
throw new NotImplementedException("NYI");
}
public Expression GetEffectiveAddress(MachineOperand op)
{
var mem = op as MemoryOperand;
if (mem != null)
{
if (mem.Base == null)
{
return mem.Offset;
}
else if (mem.Base == Registers.pc)
{
return di.Address + mem.Offset.ToInt32();
}
else if (mem.Offset == null)
{
return frame.EnsureRegister(mem.Base);
}
else {
return emitter.IAdd(
frame.EnsureRegister(mem.Base),
Constant.Int32(mem.Offset.ToInt32()));
}
}
var addrOp = di.op1 as AddressOperand;
if (addrOp != null)
{
return addrOp.Address;
}
var indIdx = di.op1 as IndirectIndexedOperand;
if (indIdx != null)
{
var a = frame.EnsureRegister(indIdx.ARegister);
var x = frame.EnsureRegister(indIdx.XRegister);
return emitter.IAdd(a, x); //$REVIEW: woefully incomplete...
}
throw new NotImplementedException(string.Format("{0} ({1})", op, op.GetType().Name));
}
public void Lea(MachineOperand ea, RegisterOperand aReg)
{
Emit(0x41C0 | Ea(ea, 0) | AReg(aReg) << 9);
}
public void Cmpa_l(MachineOperand eaSrc, RegisterOperand aDst)
{
Emit(0xB1C0 | Ea(eaSrc, 0) | AReg(aDst) << 9);
}
public void Jsr(MachineOperand op)
{
Emit(0x4E80 | Ea(op, 0));
}
public void Clr_l(MachineOperand ea)
{
Emit(0x4280 | Ea(ea, 0));
}
public void Cmp_l(MachineOperand eaSrc, RegisterOperand dDst)
{
Emit(0xB080 | Ea(eaSrc, 0) | DReg(dDst) << 9);
}
public void Bchg(int c, MachineOperand eaDst)
{
Emit(0x0840 | Ea(eaDst));
Emitter.EmitBeUInt16(c);
}
public void Bchg(RegisterOperand dSrc, MachineOperand eaDst)
{
Emit(0x0140 | DReg(dSrc) << 9 | Ea(eaDst));
}
public void Addq_l(int c, MachineOperand eaDst)
{
Emit(0x5080 | Ea(eaDst) & 0x3F | (SmallQ(c) << 9));
}
public void Addi_w(int c, MachineOperand eaDst)
{
constants.Add((ushort) c);
Emit(0x0640 | Ea(eaDst));
}
public void Adda_w(MachineOperand eaSrc, RegisterOperand aDst)
{
Emit(0xD0C0 | Ea(eaSrc, 0) | AReg(aDst) << 9);
}
public void Move_l(MachineOperand src, MachineOperand dst)
{
var eaSrc = Ea(src);
var eaDst = SwapEa(dst);
Emit(0x2000 | eaSrc | (eaDst << 6));
}
public void Subq_l(int q, MachineOperand eaDst)
{
Emit(0x5180 | SmallQ(q) << 9 | Ea(eaDst));
}
internal void Pea(MachineOperand ea)
{
//$BUG: check for valid ea's
Emit(0x4840 | Ea(ea));
}
public void Add_w(MachineOperand eaSrc, RegisterOperand dDst)
{
Emit(0xD040 | Ea(eaSrc, 0) | DReg(dDst) << 9);
}
private int Ea(MachineOperand op, int shift)
{
return Ea(op) << shift;
}
public void Add_l(RegisterOperand dSrc, MachineOperand eaDst)
{
Emit(0xD080 | Ea(eaDst, 0) | DReg(dSrc) << 9);
}
